linux-kernel - Re: [PATCH v3 10/10] riscv: dts: eswin: add HiFive Premier P550 board device tree

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <096a8318629dea9073ad6c4807a2f1dedc6b0cd6.camel@collabora.com>
Date: Tue, 15 Apr 2025 09:39:21 +0200
From: Sjoerd Simons <sjoerd@...labora.com>
To: Samuel Holland <samuel.holland@...ive.com>, Ariel D'Alessandro	
 <ariel.dalessandro@...labora.com>, Pinkesh Vaghela	
 <pinkesh.vaghela@...fochips.com>, Conor Dooley <conor@...nel.org>, Rob
 Herring	 <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
 Thomas Gleixner	 <tglx@...utronix.de>
Cc: Paul Walmsley <paul.walmsley@...ive.com>, Palmer Dabbelt	
 <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>, Daniel Lezcano	
 <daniel.lezcano@...aro.org>, Min Lin <linmin@...incomputing.com>, Pritesh
 Patel	 <pritesh.patel@...fochips.com>, Yangyu Chen <cyy@...self.name>, Lad
 Prabhakar	 <prabhakar.mahadev-lad.rj@...renesas.com>, Yu Chien Peter Lin	
 <peterlin@...estech.com>, Charlie Jenkins <charlie@...osinc.com>, Kanak
 Shilledar <kanakshilledar@...il.com>, Darshan Prajapati
 <darshan.prajapati@...fochips.com>, Neil Armstrong
 <neil.armstrong@...aro.org>, Heiko Stuebner <heiko@...ech.de>, Aradhya
 Bhatia	 <a-bhatia1@...com>, rafal@...ecki.pl, Anup Patel
 <anup@...infault.org>, 	devicetree@...r.kernel.org,
 linux-riscv@...ts.infradead.org, 	linux-kernel@...r.kernel.org,
 "kernel@...labora.com" <kernel@...labora.com>
Subject: Re: [PATCH v3 10/10] riscv: dts: eswin: add HiFive Premier P550
 board device tree

Hey,

On Mon, 2025-04-14 at 11:00 -0500, Samuel Holland wrote:
> Hi Ariel,
> 
> On 2025-04-14 7:55 AM, Ariel D'Alessandro wrote:
> > Hi Pinkesh,
> > 
> > On 4/10/25 12:25 PM, Pinkesh Vaghela wrote:
> > > From: Min Lin <linmin@...incomputing.com>
> > 
<snip>

> > Although commit log says that this includes DRAM configuration, looks like
> > it's
> > missing? In order to test this patchset, had to add this following memory
> > definition (picked from vendor kernel repository):
> > 
> >     L50: memory@...00000 {
> >             compatible = "sifive,axi4-mem-port", "sifive,axi4-port",
> > "sifive,mem-port";
> >             device_type = "memory";
> >             reg = <0x0 0x80000000 0x7f 0x80000000>;
> >             sifive,port-width-bytes = <32>;
> >     };
> 
> That is a misstatement in the commit message. The memory node is not included
> in
> the static devicetree because the amount of RAM installed on the board is
> variable. It is the responsibility of firmware to provide the memory map,
> either
> through EFI or by patching the memory node into the DT at runtime. I believe
> the
> current BSP U-Boot does the former but not the latter.

Amount of RAM being variable is pretty common on devices using FDT these days;
Typically the dts still gets a memory node that's a reasonable default, with the
expectation that e.g. u-boot will fix it up. If you look at other risc-v
devicetrees in upstream they (almost?) all come with a pre-defined memory node.
For the P550 board a default memory node for 16G ram seems reasonable (as that
seems the minimal SKU?)

That all being said. Indeed the sifive BSP u-boot doesn't seem to call the
relevant `fdt_fixup_memory` to fixup the memory node, hence us having issues
booting with u-boot directly (without going through EFI). Honestly this was a
bit of a surprise to me as only most other architectures that's just done by
common code, but that doesn't seem to be the case for risc-v (either upstream or
downstream)

-- 
Sjoerd Simons
Collabora