linux-kernel - Re: [Patch v3 12/22] perf/x86/intel: Update dyn_constranit base on PEBS event precise level

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <a3269f8a-aff3-4f9e-8f43-b00fee03121a@linux.intel.com>
Date: Wed, 16 Apr 2025 09:46:51 +0800
From: "Mi, Dapeng" <dapeng1.mi@...ux.intel.com>
To: "Liang, Kan" <kan.liang@...ux.intel.com>,
 Peter Zijlstra <peterz@...radead.org>
Cc: Ingo Molnar <mingo@...hat.com>, Arnaldo Carvalho de Melo
 <acme@...nel.org>, Namhyung Kim <namhyung@...nel.org>,
 Ian Rogers <irogers@...gle.com>, Adrian Hunter <adrian.hunter@...el.com>,
 Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
 Andi Kleen <ak@...ux.intel.com>, Eranian Stephane <eranian@...gle.com>,
 linux-kernel@...r.kernel.org, linux-perf-users@...r.kernel.org,
 Dapeng Mi <dapeng1.mi@...el.com>
Subject: Re: [Patch v3 12/22] perf/x86/intel: Update dyn_constranit base on
 PEBS event precise level


On 4/16/2025 12:31 AM, Liang, Kan wrote:
>
> On 2025-04-15 9:53 a.m., Peter Zijlstra wrote:
>> On Tue, Apr 15, 2025 at 11:44:18AM +0000, Dapeng Mi wrote:
>>> arch-PEBS provides CPUIDs to enumerate which counters support PEBS
>>> sampling and precise distribution PEBS sampling. Thus PEBS constraints
>>> should be dynamically configured base on these counter and precise
>>> distribution bitmap instead of defining them statically.
>>>
>>> Update event dyn_constraint base on PEBS event precise level.
>> What if any constraints are there on this? 
> Do you mean the static constraints defined in the
> event_constraints/pebs_constraints?
>
>> CPUID is virt host
>> controlled, right, so these could be the most horrible masks ever.
>>
> Yes, it could be changed by VMM. A sanity check should be required if
> abad mask is given.

Yes, we need a check to restrict the PEBS counter mask into the valid
counter mask, and just realized that we can't use hybrid(event->pmu,
intel_ctrl) to check counter mask and need a minor tweak since it includes
the GLOBAL_CTRL_EN_PERF_METRICS bit.

How about this?

        if (x86_pmu.arch_pebs) {
            u64 cntr_mask = hybrid(event->pmu, intel_ctrl) &
                        ~GLOBAL_CTRL_EN_PERF_METRICS;
            u64 pebs_mask = event->attr.precise_ip >= 3 ?
                        pebs_cap.pdists : pebs_cap.counters;
            if (pebs_mask != cntr_mask)
                event->hw.dyn_constraint = pebs_mask & cntr_mask;
        }


>
>> This can land us in EVENT_CONSTRAINT_OVERLAP territory, no?The dyn_constraint is a supplement of the static constraints. It doesn't
> overwrite the static constraints.
>
> In the intel_get_event_constraints(), perf always gets the static
> constraints first. If the dyn_constraint is defined, it gets the common
> mask of the static constraints and the dynamic constraints. All
> constraint rules will be complied.
>
> 	if (event->hw.dyn_constraint != ~0ULL) {
> 		c2 = dyn_constraint(cpuc, c2, idx);
> 		c2->idxmsk64 &= event->hw.dyn_constraint;
> 		c2->weight = hweight64(c2->idxmsk64);
> 	}
>
> Thanks,
> Kan
>