linux-kernel - Re: [PATCH 2/2] arm64: errata: Work around AmpereOne's erratum AC04_CPU

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Message-ID: <86mscfyadf.fsf@scott-ph-mail.amperecomputing.com>
Date: Wed, 16 Apr 2025 16:06:36 -0700
From: D Scott Phillips <scott@...amperecomputing.com>
To: Marc Zyngier <maz@...nel.org>
Cc: Oliver Upton <oliver.upton@...ux.dev>, Catalin Marinas
 <catalin.marinas@....com>, James Clark <james.clark@...aro.org>, James
 Morse <james.morse@....com>, Joey Gouly <joey.gouly@....com>, Kevin
 Brodsky <kevin.brodsky@....com>, Mark Brown <broonie@...nel.org>, Mark
 Rutland <mark.rutland@....com>, "Rob Herring
 (Arm)" <robh@...nel.org>, Shameer Kolothum
 <shameerali.kolothum.thodi@...wei.com>, Shiqi Liu <shiqiliu@...t.edu.cn>,
 Will Deacon <will@...nel.org>, Yicong Yang <yangyicong@...ilicon.com>,
 kvmarm@...ts.linux.dev, linux-arm-kernel@...ts.infradead.org, open list
 <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 2/2] arm64: errata: Work around AmpereOne's erratum
 AC04_CPU_23

Marc Zyngier <maz@...nel.org> writes:

> On Tue, 15 Apr 2025 23:13:43 +0100,
> D Scott Phillips <scott@...amperecomputing.com> wrote:
>> 
>> Marc Zyngier <maz@...nel.org> writes:
>> 
>> > On Tue, 15 Apr 2025 16:47:11 +0100,
>> > If the write to HCR_EL2 can corrupt translations, what guarantees that
>> > such write placed on a page boundary (therefore requiring another TLB
>> > lookup to continue in sequence) will be able to get to the ISB?
>> 
>> Hi Marc, I understand now from the core team that an ISB on another page
>> will be ok as the problem is on the data side only.
>
> Are you guaranteed that a younger data access can't be hoisted up and
> affect things similarly? I don't see anything that would prevent this.

Yes that's my understanding, that the younger instructions
(mis-speculated or not) can't have their window for corruption of a
translation line up with the store to HCR due to the ISB.