linux-kernel - Re: [PATCH 2/2] arm64: errata: Work around AmpereOne's erratum AC04_CPU

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Message-ID: <86y0w0k2c7.wl-maz@kernel.org>
Date: Wed, 16 Apr 2025 08:11:36 +0100
From: Marc Zyngier <maz@...nel.org>
To: D Scott Phillips <scott@...amperecomputing.com>
Cc: Oliver Upton <oliver.upton@...ux.dev>,
	Catalin Marinas <catalin.marinas@....com>,
	James Clark
 <james.clark@...aro.org>,
	James Morse <james.morse@....com>,
	Joey Gouly
 <joey.gouly@....com>,
	Kevin Brodsky <kevin.brodsky@....com>,
	Mark Brown
 <broonie@...nel.org>,
	Mark Rutland <mark.rutland@....com>,
	"Rob Herring\
 (Arm)" <robh@...nel.org>,
	Shameer Kolothum
 <shameerali.kolothum.thodi@...wei.com>,
	Shiqi Liu <shiqiliu@...t.edu.cn>,
	Will Deacon <will@...nel.org>,
	Yicong Yang <yangyicong@...ilicon.com>,
	kvmarm@...ts.linux.dev,
	linux-arm-kernel@...ts.infradead.org,
	open list
 <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 2/2] arm64: errata: Work around AmpereOne's erratum AC04_CPU_23

On Tue, 15 Apr 2025 23:13:43 +0100,
D Scott Phillips <scott@...amperecomputing.com> wrote:
> 
> Marc Zyngier <maz@...nel.org> writes:
> 
> > On Tue, 15 Apr 2025 16:47:11 +0100,
> > If the write to HCR_EL2 can corrupt translations, what guarantees that
> > such write placed on a page boundary (therefore requiring another TLB
> > lookup to continue in sequence) will be able to get to the ISB?
> 
> Hi Marc, I understand now from the core team that an ISB on another page
> will be ok as the problem is on the data side only.

Are you guaranteed that a younger data access can't be hoisted up and
affect things similarly? I don't see anything that would prevent this.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.