linux-kernel - Re: [PATCH 1/4] clk: renesas: r9a09g047: Add clock and reset entries for GE3D

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Message-ID: <CAMuHMdVdvcPA_Wsmc6NZ4oQbVoFzHjGCKnZfc5aN4uZjkpYWnw@mail.gmail.com>
Date: Wed, 16 Apr 2025 11:57:10 +0200
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Tommaso Merciai <tommaso.merciai.xr@...renesas.com>
Cc: tomm.merciai@...il.com, linux-renesas-soc@...r.kernel.org, 
	biju.das.jz@...renesas.com, Geert Uytterhoeven <geert+renesas@...der.be>, 
	Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, linux-clk@...r.kernel.org, 
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/4] clk: renesas: r9a09g047: Add clock and reset entries
 for GE3D

Hi Tommaso,

On Wed, 2 Apr 2025 at 15:12, Tommaso Merciai
<tommaso.merciai.xr@...renesas.com> wrote:
> Add CLK_PLLVDO_GPU along with the necessary clock and reset entries for
> GE3D.
>
> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@...renesas.com>

Thanks for your patch!

> --- a/drivers/clk/renesas/r9a09g047-cpg.c
> +++ b/drivers/clk/renesas/r9a09g047-cpg.c
> @@ -185,6 +187,12 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
>                                                 BUS_MSTOP(9, BIT(4))),
>         DEF_MOD("tsu_1_pclk",                   CLK_QEXTAL, 16, 10, 8, 10,
>                                                 BUS_MSTOP(2, BIT(15))),
> +       DEF_MOD("ge3d_clk",                     CLK_PLLVDO_GPU, 15, 0, 7, 16,
> +                                               BUS_MSTOP(3, BIT(4))),
> +       DEF_MOD("ge3d_axi_clk",                 CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17,
> +                                               BUS_MSTOP(3, BIT(4))),
> +       DEF_MOD("ge3d_ace_clk",                 CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18,
> +                                               BUS_MSTOP(3, BIT(4))),

Moving up to preserve sort order (by CPG_CLKON module number).

>  };
>
>  static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
> @@ -214,6 +222,9 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
>         DEF_RST(12, 6, 5, 23),          /* CRU_0_ARESETN */
>         DEF_RST(12, 7, 5, 24),          /* CRU_0_S_RESETN */
>         DEF_RST(15, 8, 7, 9),           /* TSU_1_PRESETN */
> +       DEF_RST(13, 13, 6, 14),         /* GE3D_0_RESETN */
> +       DEF_RST(13, 14, 6, 15),         /* GE3D_0_AXI_RESETN */
> +       DEF_RST(13, 15, 6, 16),         /* GE3D_0_ACE_RESETN */

Moving up to preserve sort order (by CPF_RST module number).
The documentation does not have the "_0" part in the reset names,
so I will drop these while applying, too.

>  };
>
>  const struct rzv2h_cpg_info r9a09g047_cpg_info __initconst = {

Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>
i.e. will queue in renesas-clk for v6.16 with the above fixed.

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds