linux-kernel - [PATCH 1/5] dt-bindings: mfd: add bindings for NVIDIA VRS PSEQ

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20250416120619.483793-2-shgarg@nvidia.com>
Date: Wed, 16 Apr 2025 12:06:15 +0000
From: Shubhi Garg <shgarg@...dia.com>
To: <lee@...nel.org>, <alexandre.belloni@...tlin.com>,
	<thierry.reding@...il.com>, <jonathanh@...dia.com>,
	<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
	<linux-tegra@...r.kernel.org>
CC: <shgarg@...dia.com>
Subject: [PATCH 1/5] dt-bindings: mfd: add bindings for NVIDIA VRS PSEQ

Add bindings for NVIDIA VRS (Voltage Regulator Specification) power
sequencer device. NVIDIA VRS PSEQ controls ON/OFF and suspend/resume
power sequencing of system power rails on Tegra234 SoC. This device
also provides 32kHz RTC support with backup battery for system timing.

Signed-off-by: Shubhi Garg <shgarg@...dia.com>
---
 .../bindings/mfd/nvidia,vrs-pseq.yaml         | 61 +++++++++++++++++++
 1 file changed, 61 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mfd/nvidia,vrs-pseq.yaml

diff --git a/Documentation/devicetree/bindings/mfd/nvidia,vrs-pseq.yaml b/Documentation/devicetree/bindings/mfd/nvidia,vrs-pseq.yaml
new file mode 100644
index 000000000000..d4c5984930e9
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/nvidia,vrs-pseq.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/nvidia,vrs-pseq.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Voltage Regulator Specification Power Sequencer
+
+maintainers:
+  - Shubhi Garg <shgarg@...dia.com>
+
+description:
+  NVIDIA Voltage Regulator Specification Power Sequencer device controls ON/OFF
+  and suspend/resume power sequencing of system power rails for NVIDIA
+  SoCs. It provides 32kHz RTC clock support with backup battery for
+  system timing.
+
+properties:
+  compatible:
+    const: nvidia,vrs-pseq
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  interrupt-controller: true
+
+  '#interrupt-cells':
+    const: 2
+    description:
+      The first cell is the IRQ number, the second cell is the trigger type.
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - interrupt-controller
+  - "#interrupt-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    i2c {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        vrs@3c {
+            compatible = "nvidia,vrs-pseq";
+            reg = <0x3c>;
+            interrupt-parent = <&pmc>;
+            interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
+            interrupt-controller;
+            #interrupt-cells = <2>;
+            status = "disabled";
+       };
+    };
-- 
2.25.1