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Message-ID: <CA+V-a8sMVGjzdEiBNha8WsubZGyFrCXQDhbyUBvFqbdn3pSJvw@mail.gmail.com>
Date: Thu, 17 Apr 2025 14:58:38 +0100
From: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To: Geert Uytterhoeven <geert@...ux-m68k.org>
Cc: Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
Magnus Damm <magnus.damm@...il.com>, linux-renesas-soc@...r.kernel.org,
linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, Biju Das <biju.das.jz@...renesas.com>,
Fabrizio Castro <fabrizio.castro.jz@...esas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH v2 9/9] clk: renesas: r9a09g057: Add clock and reset
entries for GBETH0/1
Hi Geert,
On Wed, Apr 16, 2025 at 8:37 AM Geert Uytterhoeven <geert@...ux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Tue, 15 Apr 2025 at 21:25, Lad, Prabhakar <prabhakar.csengg@...il.com> wrote:
> > On Tue, Apr 15, 2025 at 3:37 PM Geert Uytterhoeven <geert@...ux-m68k.org> wrote:
> > > On Mon, 7 Apr 2025 at 18:52, Prabhakar <prabhakar.csengg@...il.com> wrote:
> > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> > > >
> > > > Add clock and reset entries for GBETH instances. Include core clocks for
> > > > PTP, sourced from PLLETH, and add PLLs, dividers, and static mux clocks
> > > > used as clock sources for the GBETH IP.
> > > >
> > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> > >
> > > Thanks for your patch!
> > >
> > > > --- a/drivers/clk/renesas/r9a09g057-cpg.c
> > > > +++ b/drivers/clk/renesas/r9a09g057-cpg.c
> > >
> > > > @@ -78,6 +87,19 @@ static const struct clk_div_table dtable_2_64[] = {
> > > > {0, 0},
> > > > };
> > > >
> > > > +static const struct clk_div_table dtable_2_100[] = {
> > > > + {0, 2},
> > > > + {1, 10},
> > > > + {2, 100},
> > > > + {0, 0},
> > > > +};
> > > > +
> > > > +/* Mux clock tables */
> > > > +static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0-rxc-rxclk" };
> > > > +static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0-txc-txclk" };
> > > > +static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1-rxc-rxclk" };
> > > > +static const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1", "et1-txc-txclk" };
> > >
> > > The "et[01]-[rt]xc-[rt]xclk" clocks are not created by this driver.
> > > IIUIC, they are actually Ethernet PHY signals.
> > > How is this supposed to work?
> > >
> > My intention was to add support for PHY drivers to provide the clocks
> > and hook them up accordingly. Currently, for the RX clocks, we get a
> > rate of 0 since they are external.
>
> So the link would not be provided by DT?
> If these clocks are inputs to the clock controller, they should be
> listed in the clock controller's clock{,-name}s' properties...
>
> > I haven’t written a prototype yet for the PHY driver to provide the
> > clocks, but the plan is to get the initial pieces in place and then
> > extend support for that.
> >
> > Is my understanding correct that the PHY should provide the clocks? Or
> > would you suggest a different approach?
>
> The Static Mux Control Registers (CPG_SSEL[01]) registers treat them as
> clock inputs. However, Figure 6.3-1 ("Block Diagram of the Ethernet
> Interface") shows the TX clocks are bidirectional, so they can be used
> as either inputs or outputs? On RGMII[1], RXC is an input (PHY-to-MAC),
> while TXC is an output (MAC-to-PHY).
>
I think the Figure 6.3-1 shows TX clocks are bidirectional because
PFC_OEN.OEN0/1 can be used to configure input/output for the TXC
pins..
I added the below POC and did some limited testing, (not the code in
PHY driver is not complete as it still needs to check interface mode
and depending on that register one/two clocks)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
index 76e6b658077a..08d2651eba59 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
@@ -105,6 +105,50 @@ L3_CA55: cache-controller-0 {
};
};
+ et0_rxclk: et0-rxclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ /*
+ * This value must be overridden by the board depending
+ * on PHY connection
+ */
+ status = "disabled";
+ };
+
+ et0_txclk: et0-txclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ /*
+ * This value must be overridden by the board depending
+ * on PHY connection
+ */
+ status = "disabled";
+ };
+
+ et1_rxclk: et1-rxclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ /*
+ * This value must be overridden by the board depending
+ * on PHY connection
+ */
+ status = "disabled";
+ };
+
+ et1_txclk: et1-txclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ /*
+ * This value must be overridden by the board depending
+ * on PHY connection
+ */
+ status = "disabled";
+ };
+
gpu_opp_table: opp-table-1 {
compatible = "operating-points-v2";
@@ -266,8 +310,12 @@ pinctrl: pinctrl@...10000 {
cpg: clock-controller@...20000 {
compatible = "renesas,r9a09g057-cpg";
reg = <0 0x10420000 0 0x10000>;
- clocks = <&audio_extal_clk>, <&rtxin_clk>,
<&qextal_clk>;
- clock-names = "audio_extal", "rtxin", "qextal";
+ clocks = <&audio_extal_clk>, <&rtxin_clk>,
<&qextal_clk>,
+ <&et0_txclk>, <&et0_rxclk>,
+ <&et1_txclk>, <&et1_rxclk>;
+ clock-names = "audio_extal", "rtxin", "qextal",
+ "et0_txclk", "et0_rxclk",
+ "et1_txclk", "et1_rxclk";
#clock-cells = <2>;
#reset-cells = <1>;
#power-domain-cells = <0>;
diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
index d0160ae4d4cd..3f9c9cf1a468 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
@@ -136,6 +136,11 @@ &audio_extal_clk {
clock-frequency = <22579200>;
};
+&cpg {
+ clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>,
+ <&phy0 0>, <&phy0 1>, <&phy1 0>, <&phy1 1>;
+};
+
&cru0 {
status = "disabled";
};
@@ -248,6 +253,8 @@ mdio {
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id0022.1640",
"ethernet-phy-ieee802.3-c22";
+ #clock-cells = <1>;
+ clock-output-names = "et0_rxclk", "et0_txclk";
reg = <0>;
rxc-skew-psec = <0>;
txc-skew-psec = <0>;
@@ -279,6 +286,8 @@ mdio {
phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id0022.1640",
"ethernet-phy-ieee802.3-c22";
+ #clock-cells = <1>;
+ clock-output-names = "et1_rxclk", "et1_txclk";
reg = <0>;
rxc-skew-psec = <0>;
txc-skew-psec = <0>;
diff --git a/drivers/clk/renesas/r9a09g057-cpg.c
b/drivers/clk/renesas/r9a09g057-cpg.c
index 94c959577f03..5a0f0b9e62c6 100644
--- a/drivers/clk/renesas/r9a09g057-cpg.c
+++ b/drivers/clk/renesas/r9a09g057-cpg.c
@@ -23,6 +23,10 @@ enum clk_ids {
CLK_AUDIO_EXTAL,
CLK_RTXIN,
CLK_QEXTAL,
+ CLK_ET0_RXCLK,
+ CLK_ET0_TXCLK,
+ CLK_ET1_RXCLK,
+ CLK_ET1_TXCLK,
/* PLL Clocks */
CLK_PLLCM33,
@@ -128,16 +132,20 @@ static const struct clk_div_table dtable_16_128[] = {
};
/* Mux clock tables */
-static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0",
"et0-rxc-rxclk" };
-static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0",
"et0-txc-txclk" };
-static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1",
"et1-rxc-rxclk" };
-static const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1",
"et1-txc-txclk" };
+static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0_rxclk" };
+static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0_txclk" };
+static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1_rxclk" };
+static const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1", "et1_txclk" };
static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL),
DEF_INPUT("rtxin", CLK_RTXIN),
DEF_INPUT("qextal", CLK_QEXTAL),
+ DEF_INPUT("et0_rxclk", CLK_ET0_RXCLK),
+ DEF_INPUT("et0_txclk", CLK_ET0_TXCLK),
+ DEF_INPUT("et1_rxclk", CLK_ET1_RXCLK),
+ DEF_INPUT("et1_txclk", CLK_ET1_TXCLK),
/* PLL Clocks */
DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3),
diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index 71fb4410c31b..79245b81a8dc 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -20,6 +20,7 @@
*/
#include <linux/bitfield.h>
+#include <linux/clk-provider.h>
#include <linux/ethtool_netlink.h>
#include <linux/kernel.h>
#include <linux/module.h>
@@ -362,6 +363,13 @@
/* Delay used to get the second part from the LTC */
#define LAN8841_GET_SEC_LTC_DELAY (500 * NSEC_PER_MSEC)
+struct micrel_phy_clk {
+ struct phy_device *phydev;
+ struct clk_hw clk[2];
+};
+
+static struct micrel_phy_clk phy_clk;
+
struct kszphy_hw_stat {
const char *string;
u8 reg;
@@ -1527,7 +1535,11 @@ static int ksz9131_read_status(struct phy_device *phydev)
if (ret < 0)
return ret;
- return genphy_read_status(phydev);
+ ret = genphy_read_status(phydev);
+ clk_set_rate(phy_clk.clk[0].clk, rgmii_clock(phydev->speed));
+ clk_set_rate(phy_clk.clk[1].clk, rgmii_clock(phydev->speed));
+ return ret;
}
static int ksz9131_config_aneg(struct phy_device *phydev)
@@ -2272,6 +2284,41 @@ static int ksz8061_suspend(struct phy_device *phydev)
return kszphy_suspend(phydev);
}
+static struct clk_hw *kszphy_of_clk_get(struct of_phandle_args *clkspec,
+ void *data)
+{
+ unsigned int idx = clkspec->args[0];
+ struct clk_hw **clkout_hw = data;
+
+ if (idx >= ARRAY_SIZE(phy_clk.clk))
+ return ERR_PTR(-EINVAL);
+
+ return clkout_hw[idx];
+}
+
+static unsigned long phy_clk_recalc_rate(struct clk_hw *hw, unsigned
long parent_rate)
+{
+ if (phy_clk.phydev->speed == SPEED_1000)
+ return 125000000UL;
+ else if (phy_clk.phydev->speed == SPEED_100)
+ return 25000000UL;
+ else if (phy_clk.phydev->speed == SPEED_10)
+ return 2500000UL;
+ else
+ return 0;
+}
+
+static long phy_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ return clamp(rate, 2500000UL, 125000000UL);
+}
+
+static const struct clk_ops phy_clk_ops = {
+ .recalc_rate = phy_clk_recalc_rate,
+ .round_rate = phy_clk_round_rate,
+};
+
static int kszphy_probe(struct phy_device *phydev)
{
const struct kszphy_type *type = phydev->drv->driver_data;
@@ -2329,7 +2376,32 @@ static int kszphy_probe(struct phy_device *phydev)
priv->rmii_ref_clk_sel_val = true;
}
- return 0;
+ phy_clk.phydev = phydev;
+ /* Register clk outputs */
+ for (u8 i = 0; i < 2; i++) {
+ struct clk_init_data init;
+ const char *name;
+ int ret;
+
+ phy_clk.clk[i].init = &init;
+ ret = of_property_read_string_index(phydev->mdio.dev.of_node,
+ "clock-output-names",
+ i, &name);
+ if (ret) {
+ phydev_err(phydev, "Failed to get clock name %d\n", i);
+ return ret;
+ }
+ init.name = name;
+ init.ops = &phy_clk_ops;
+ init.flags = 0;
+ init.parent_names = NULL;
+ init.num_parents = 0;
+ ret = devm_clk_hw_register(&phydev->mdio.dev, &phy_clk.clk[i]);
+ if (ret)
+ return ret;
+ }
+
+ return devm_of_clk_add_hw_provider(&phydev->mdio.dev,
kszphy_of_clk_get, &phy_clk.clk);
}
static int lan8814_cable_test_start(struct phy_device *phydev)
Below are the logs:
root@...2h-evk:~# cat /sys/kernel/debug/clk/clk_summary | grep gbeth_0
gbeth_0_clk_rx_180_i 1 1 0
125000000 0 0 50000 Y 15c30000.ethernet
rx-180
gbeth_0_clk_rx_i 1 1 0
125000000 0 0 50000 Y 15c30000.ethernet
rx
gbeth_0_clk_tx_180_i 1 1 0
125000000 0 0 50000 Y
15c30000.ethernet tx-180
gbeth_0_clk_tx_i 1 1 0
125000000 0 0 50000 Y
15c30000.ethernet tx
gbeth_0_clk_ptp_ref_i 1 1 0
125000000 0 0 50000 Y
15c30000.ethernet ptp_ref
gbeth_0_aclk_i 1 1 0
200000000 0 0 50000 Y 15c30000.ethernet
stmmaceth
gbeth_0_aclk_csr_i 1 1 0
200000000 0 0 50000 Y 15c30000.ethernet
pclk
root@...2h-evk:~#
root@...2h-evk:~#
root@...2h-evk:~#
root@...2h-evk:~# [ 44.853189] kauditd_printk_skb: 5 callbacks suppressed
[ 44.853204] audit: type=1334 audit(1744888354.247:22): prog-id=18 op=UNLOAD
[ 44.865320] audit: type=1334 audit(1744888354.247:23): prog-id=17 op=UNLOAD
[ 44.872331] audit: type=1334 audit(1744888354.247:24): prog-id=16 op=UNLOAD
root@...2h-evk:~#
root@...2h-evk:~# ethtool -s end0 speed 100
[ 97.153939] renesas-gbeth 15c30000.ethernet end0: Link is Down
[ 101.258899] renesas-gbeth 15c30000.ethernet end0: Link is Up -
100Mbps/Full - flow control rx/tx
root@...2h-evk:~#
root@...2h-evk:~#
root@...2h-evk:~# cat /sys/kernel/debug/clk/clk_summary | grep gbeth_0
gbeth_0_clk_rx_180_i 1 1 0
25000000 0 0 50000 Y 15c30000.ethernet
rx-180
gbeth_0_clk_rx_i 1 1 0
25000000 0 0 50000 Y 15c30000.ethernet
rx
gbeth_0_clk_tx_180_i 1 1 0
25000000 0 0 50000 Y
15c30000.ethernet tx-180
gbeth_0_clk_tx_i 1 1 0
25000000 0 0 50000 Y
15c30000.ethernet tx
gbeth_0_clk_ptp_ref_i 1 1 0
125000000 0 0 50000 Y
15c30000.ethernet ptp_ref
gbeth_0_aclk_i 1 1 0
200000000 0 0 50000 Y 15c30000.ethernet
stmmaceth
gbeth_0_aclk_csr_i 1 1 0
200000000 0 0 50000 Y 15c30000.ethernet
pclk
root@...2h-evk:~# ethtool -s end0 speed 10
root@...2h-evk:~# [ 117.300170] renesas-gbeth 15c30000.ethernet end0:
Link is Down
[ 119.338798] renesas-gbeth 15c30000.ethernet end0: Link is Up -
10Mbps/Full - flow control rx/tx
root@...2h-evk:~# cat /sys/kernel/debug/clk/clk_summary | grep gbeth_0
gbeth_0_clk_rx_180_i 1 1 0 2500000
0 0 50000 Y 15c30000.ethernet
rx-180
gbeth_0_clk_rx_i 1 1 0 2500000
0 0 50000 Y 15c30000.ethernet
rx
gbeth_0_clk_tx_180_i 1 1 0 2500000
0 0 50000 Y 15c30000.ethernet
tx-180
gbeth_0_clk_tx_i 1 1 0 2500000
0 0 50000 Y 15c30000.ethernet
tx
gbeth_0_clk_ptp_ref_i 1 1 0
125000000 0 0 50000 Y
15c30000.ethernet ptp_ref
gbeth_0_aclk_i 1 1 0
200000000 0 0 50000 Y 15c30000.ethernet
stmmaceth
gbeth_0_aclk_csr_i 1 1 0
200000000 0 0 50000 Y 15c30000.ethernet
pclk
Cheers,
Prabhakar
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