[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-Id: <174488932359.908730.13983605983506218156.b4-ty@kernel.org>
Date: Thu, 17 Apr 2025 15:27:26 +0100
From: Will Deacon <will@...nel.org>
To: iommu@...ts.linux.dev,
Balbir Singh <balbirs@...dia.com>
Cc: catalin.marinas@....com,
kernel-team@...roid.com,
Will Deacon <will@...nel.org>,
linux-kernel@...r.kernel.org,
Jean-Philippe Brucker <jean-philippe@...aro.org>,
Robin Murphy <robin.murphy@....com>,
Joerg Roedel <joro@...tes.org>,
Jason Gunthorpe <jgg@...pe.ca>
Subject: Re: [PATCH] iommu/arm-smmu-v3: Fix pgsize_bit for sva domains
On Sat, 12 Apr 2025 10:23:54 +1000, Balbir Singh wrote:
> UBSan caught a bug with IOMMU SVA domains, where the reported exponent
> value in __arm_smmu_tlb_inv_range() was >= 64.
> __arm_smmu_tlb_inv_range() uses the domain's pgsize_bitmap to compute
> the number of pages to invalidate and the invalidation range. Currently
> arm_smmu_sva_domain_alloc() does not setup the iommu domain's
> pgsize_bitmap. This leads to __ffs() on the value returning 64 and that
> leads to undefined behaviour w.r.t. shift operations
>
> [...]
Applied to iommu (arm/smmu/fixes), thanks!
[1/1] iommu/arm-smmu-v3: Fix pgsize_bit for sva domains
https://git.kernel.org/iommu/c/12f78021973a
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev
Powered by blists - more mailing lists