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Message-ID: <20250417085948.35b0ec5a@kernel.org>
Date: Thu, 17 Apr 2025 08:59:48 -0700
From: Jakub Kicinski <kuba@...nel.org>
To: Daniel Golle <daniel@...rotopia.org>
Cc: Felix Fietkau <nbd@....name>, Sean Wang <sean.wang@...iatek.com>,
Lorenzo Bianconi <lorenzo@...nel.org>, Andrew Lunn <andrew+netdev@...n.ch>,
"David S. Miller" <davem@...emloft.net>, Eric Dumazet
<edumazet@...gle.com>, Paolo Abeni <pabeni@...hat.com>, Matthias Brugger
<matthias.bgg@...il.com>, AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>, Florian Fainelli
<f.fainelli@...il.com>, netdev@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org
Subject: Re: [PATCH net v2 4/5] net: ethernet: mtk_eth_soc: net: revise
NETSYSv3 hardware configuration
On Thu, 17 Apr 2025 16:45:14 +0100 Daniel Golle wrote:
> On Thu, Apr 17, 2025 at 08:10:55AM -0700, Jakub Kicinski wrote:
> > On Wed, 16 Apr 2025 01:51:42 +0100 Daniel Golle wrote:
> > > + /* PSE should not drop port8, port9 and port13 packets from WDMA Tx */
> > > + mtk_w32(eth, 0x00002300, PSE_DROP_CFG);
> > > +
> > > + /* PSE should drop packets to port8, port9 and port13 on WDMA Rx ring full */
> >
> > nit: please try to wrap at 80 chars. There's really no need to go over
> > on comments. Some of us stick to 80 char terminals.
>
> Too late now to send another revision...
I only applied the first 3 :)
> > > [...]
> > > diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
> > > index 39709649ea8d1..eaa96c8483b70 100644
> > > --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
> > > +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
> > > @@ -151,7 +151,12 @@
> > > #define PSE_FQFC_CFG1 0x100
> > > #define PSE_FQFC_CFG2 0x104
> > > #define PSE_DROP_CFG 0x108
> > > -#define PSE_PPE0_DROP 0x110
> > > +#define PSE_PPE_DROP(x) (0x110 + ((x) * 0x4))
> > > +
> > > +/* PSE Last FreeQ Page Request Control */
> > > +#define PSE_DUMY_REQ 0x10C
> >
> > This really looks like misspelling of DUMMY, is it really supposed
> > to have one 'M' ?
>
> I also thought that when I first saw that and have told MediaTek engineers
> about it, they told me that the register is called like that also in their
> datasheet and hence they want the name to be consistent in the driver.
Hm, maybe add a comment ? It confused both of us, probably going
to confuse most people later on
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