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Message-ID: <20250417-bxs-4-64-dts-v2-1-9f8c09233114@imgtec.com>
Date: Thu, 17 Apr 2025 10:10:02 +0100
From: Matt Coster <matt.coster@...tec.com>
To: Nishanth Menon <nm@...com>, Vignesh Raghavendra <vigneshr@...com>,
"Tero
Kristo" <kristo@...nel.org>, Rob Herring <robh@...nel.org>,
"Krzysztof
Kozlowski" <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>
CC: <linux-arm-kernel@...ts.infradead.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, Frank Binns <frank.binns@...tec.com>,
"Alessio Belle" <alessio.belle@...tec.com>,
Alexandru Dadu
<alexandru.dadu@...tec.com>,
Luigi Santivetti <luigi.santivetti@...tec.com>,
Randolph Sapp <rs@...com>, Darren Etheridge <detheridge@...com>,
Matt Coster
<matt.coster@...tec.com>
Subject: [PATCH v2 1/2] arm64: dts: ti: k3-am62: New GPU binding details
Use the new compatible string and power domain name as introduced in
commit 2c01d9099859 ("dt-bindings: gpu: img: Future-proofing
enhancements")[1].
[1]: https://lore.kernel.org/r/20250410-sets-bxs-4-64-patch-v1-v6-1-eda620c5865f@imgtec.com
Reviewed-by: Randolph Sapp <rs@...com>
Signed-off-by: Matt Coster <matt.coster@...tec.com>
---
Changes in v2:
- Add Randolph's Rb
- Link to v1: https://lore.kernel.org/r/20250415-bxs-4-64-dts-v1-1-f7d3fa06625d@imgtec.com
This patch was previously sent as [DO NOT MERGE]:
https://lore.kernel.org/r/20250410-sets-bxs-4-64-patch-v1-v6-17-eda620c5865f@imgtec.com
---
arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
index 7d355aa73ea2116723735f70b9351cefcd8bc118..d17b25cae196b08d24adbe7c913ccaba7eed37eb 100644
--- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
@@ -691,12 +691,14 @@ ospi0: spi@...0000 {
};
gpu: gpu@...0000 {
- compatible = "ti,am62-gpu", "img,img-axe";
+ compatible = "ti,am62-gpu", "img,img-axe-1-16m", "img,img-axe",
+ "img,img-rogue";
reg = <0x00 0x0fd00000 0x00 0x20000>;
clocks = <&k3_clks 187 0>;
clock-names = "core";
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
+ power-domain-names = "a";
};
cpsw3g: ethernet@...0000 {
--
2.49.0
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