linux-kernel - Re: [PATCH v8 16/16] CXL/PCI: Disable CXL protocol errors during CXL Port cleanup

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Message-ID: <20250417111309.00000672@huawei.com>
Date: Thu, 17 Apr 2025 11:13:09 +0100
From: Jonathan Cameron <Jonathan.Cameron@...wei.com>
To: "Bowman, Terry" <terry.bowman@....com>
CC: <linux-cxl@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
	<linux-pci@...r.kernel.org>, <nifan.cxl@...il.com>, <dave@...olabs.net>,
	<dave.jiang@...el.com>, <alison.schofield@...el.com>,
	<vishal.l.verma@...el.com>, <dan.j.williams@...el.com>,
	<bhelgaas@...gle.com>, <mahesh@...ux.ibm.com>, <ira.weiny@...el.com>,
	<oohall@...il.com>, <Benjamin.Cheatham@....com>, <rrichter@....com>,
	<nathan.fontenot@....com>, <Smita.KoralahalliChannabasappa@....com>,
	<lukas@...ner.de>, <ming.li@...omail.com>,
	<PradeepVineshReddy.Kodamati@....com>
Subject: Re: [PATCH v8 16/16] CXL/PCI: Disable CXL protocol errors during
 CXL Port cleanup

Hi Terry,

> >> diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c
> >> index d3068f5cc767..d1ef0c676ff8 100644
> >> --- a/drivers/pci/pcie/aer.c
> >> +++ b/drivers/pci/pcie/aer.c
> >> @@ -977,6 +977,31 @@ void pci_aer_unmask_internal_errors(struct pci_dev *dev)
> >>  }
> >>  EXPORT_SYMBOL_NS_GPL(pci_aer_unmask_internal_errors, "CXL");
> >>  
> >> +/**
> >> + * pci_aer_mask_internal_errors - mask internal errors
> >> + * @dev: pointer to the pcie_dev data structure
> >> + *
> >> + * Masks internal errors in the Uncorrectable and Correctable Error
> >> + * Mask registers.
> >> + *
> >> + * Note: AER must be enabled and supported by the device which must be
> >> + * checked in advance, e.g. with pcie_aer_is_native().
> >> + */
> >> +void pci_aer_mask_internal_errors(struct pci_dev *dev)
> >> +{
> >> +	int aer = dev->aer_cap;
> >> +	u32 mask;
> >> +
> >> +	pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &mask);
> >> +	mask |= PCI_ERR_UNC_INTN;
> >> +	pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, mask);
> >> +  
> > It does an extra clear we don't need, but....
> > 	pci_clear_and_set_config_dword(dev, aer + PCI_ERR_UNCOR_MASK,
> > 				       0, PCI_ERR_UNC_INTN);
> >
> > 	is at very least shorter than the above 3 lines.  
> Doing so will overwrite the existing mask. CXL normally only uses AER UIE/CIE but if the device
> happens to lose alternate training and no longer identifies as a CXL device than this mask
> value would be critical for reporting PCI AER errors and would need UCE/CE enabled (other
> than UIE/CIE).
I'm not seeing that.  Implementation of pci_clear_and_set_config_dword() is:
void pci_clear_and_set_config_dword(const struct pci_dev *dev, int pos,
				    u32 clear, u32 set)
{
	u32 val;

	pci_read_config_dword(dev, pos, &val);
	val &= ~clear;
	val |= set;
	pci_write_config_dword(dev, pos, val);
}

With clear parameter as zero it will do the same the open coded
version you have above as the ~clear will be all 1s and hence
&= ~clear has no affect.

Arguably we could add pci_clear_config_dword() and pci_set_config_dword()
that both take one fewer parameter but I guess that is not worth
the bother.

Jonathan