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Message-ID: <20250418184658.456398-5-prabhakar.mahadev-lad.rj@bp.renesas.com>
Date: Fri, 18 Apr 2025 19:46:47 +0100
From: Prabhakar <prabhakar.csengg@...il.com>
To: Andrzej Hajda <andrzej.hajda@...el.com>,
Neil Armstrong <neil.armstrong@...aro.org>,
Robert Foss <rfoss@...nel.org>,
Laurent Pinchart <Laurent.pinchart@...asonboard.com>,
Jonas Karlman <jonas@...boo.se>,
Jernej Skrabec <jernej.skrabec@...il.com>,
David Airlie <airlied@...il.com>,
Simona Vetter <simona@...ll.ch>,
Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Maxime Ripard <mripard@...nel.org>,
Thomas Zimmermann <tzimmermann@...e.de>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Biju Das <biju.das.jz@...renesas.com>,
Geert Uytterhoeven <geert+renesas@...der.be>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Philipp Zabel <p.zabel@...gutronix.de>,
Magnus Damm <magnus.damm@...il.com>
Cc: dri-devel@...ts.freedesktop.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
linux-renesas-soc@...r.kernel.org,
linux-clk@...r.kernel.org,
Prabhakar <prabhakar.csengg@...il.com>,
Fabrizio Castro <fabrizio.castro.jz@...esas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>,
Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Subject: [PATCH v3 04/15] dt-bindings: display: bridge: renesas,dsi: Add support for RZ/V2H(P) SoC
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
The MIPI DSI interface on the RZ/V2H(P) SoC is nearly identical to that of
the RZ/G2L SoC. While the LINK registers are the same for both SoCs, the
D-PHY registers differ. Additionally, the number of resets for DSI on
RZ/V2H(P) is two compared to three on the RZ/G2L.
To accommodate these differences, a SoC-specific
`renesas,r9a09g057-mipi-dsi` compatible string has been added for the
RZ/V2H(P) SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
---
v2->v3:
- No changes
v1->v2:
- Added enum for RZ/V2H as suggested by Krzysztof as the list
will grow in the future (while adding RZ/G3E SoC).
- Added Reviewed-by tag from Krzysztof.
---
.../bindings/display/bridge/renesas,dsi.yaml | 116 +++++++++++++-----
1 file changed, 87 insertions(+), 29 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
index e08c24633926..5980df2b389b 100644
--- a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
+++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
@@ -14,16 +14,17 @@ description: |
RZ/G2L alike family of SoC's. The encoder can operate in DSI mode, with
up to four data lanes.
-allOf:
- - $ref: /schemas/display/dsi-controller.yaml#
-
properties:
compatible:
- items:
+ oneOf:
- enum:
- - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC}
- - renesas,r9a07g054-mipi-dsi # RZ/V2L
- - const: renesas,rzg2l-mipi-dsi
+ - renesas,r9a09g057-mipi-dsi # RZ/V2H(P)
+
+ - items:
+ - enum:
+ - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC}
+ - renesas,r9a07g054-mipi-dsi # RZ/V2L
+ - const: renesas,rzg2l-mipi-dsi
reg:
maxItems: 1
@@ -49,34 +50,56 @@ properties:
- const: debug
clocks:
- items:
- - description: DSI D-PHY PLL multiplied clock
- - description: DSI D-PHY system clock
- - description: DSI AXI bus clock
- - description: DSI Register access clock
- - description: DSI Video clock
- - description: DSI D-PHY Escape mode transmit clock
+ oneOf:
+ - items:
+ - description: DSI D-PHY PLL multiplied clock
+ - description: DSI D-PHY system clock
+ - description: DSI AXI bus clock
+ - description: DSI Register access clock
+ - description: DSI Video clock
+ - description: DSI D-PHY Escape mode transmit clock
+ - items:
+ - description: DSI D-PHY PLL multiplied clock
+ - description: DSI AXI bus clock
+ - description: DSI Register access clock
+ - description: DSI Video clock
+ - description: DSI D-PHY Escape mode transmit clock
clock-names:
- items:
- - const: pllclk
- - const: sysclk
- - const: aclk
- - const: pclk
- - const: vclk
- - const: lpclk
+ oneOf:
+ - items:
+ - const: pllclk
+ - const: sysclk
+ - const: aclk
+ - const: pclk
+ - const: vclk
+ - const: lpclk
+ - items:
+ - const: pllclk
+ - const: aclk
+ - const: pclk
+ - const: vclk
+ - const: lpclk
resets:
- items:
- - description: MIPI_DSI_CMN_RSTB
- - description: MIPI_DSI_ARESET_N
- - description: MIPI_DSI_PRESET_N
+ oneOf:
+ - items:
+ - description: MIPI_DSI_CMN_RSTB
+ - description: MIPI_DSI_ARESET_N
+ - description: MIPI_DSI_PRESET_N
+ - items:
+ - description: MIPI_DSI_ARESET_N
+ - description: MIPI_DSI_PRESET_N
reset-names:
- items:
- - const: rst
- - const: arst
- - const: prst
+ oneOf:
+ - items:
+ - const: rst
+ - const: arst
+ - const: prst
+ - items:
+ - const: arst
+ - const: prst
power-domains:
maxItems: 1
@@ -130,6 +153,41 @@ required:
additionalProperties: false
+allOf:
+ - $ref: ../dsi-controller.yaml#
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r9a09g057-mipi-dsi
+ then:
+ properties:
+ clocks:
+ maxItems: 5
+
+ clock-names:
+ maxItems: 5
+
+ resets:
+ maxItems: 2
+
+ reset-names:
+ maxItems: 2
+ else:
+ properties:
+ clocks:
+ minItems: 6
+
+ clock-names:
+ minItems: 6
+
+ resets:
+ minItems: 3
+
+ reset-names:
+ minItems: 3
+
examples:
- |
#include <dt-bindings/clock/r9a07g044-cpg.h>
--
2.49.0
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