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Message-Id: <20250418053239.4351-6-cyan.yang@sifive.com>
Date: Fri, 18 Apr 2025 13:32:32 +0800
From: Cyan Yang <cyan.yang@...ive.com>
To: robh@...nel.org,
krzk+dt@...nel.org,
conor+dt@...nel.org,
corbet@....net,
paul.walmsley@...ive.com,
palmer@...belt.com,
aou@...s.berkeley.edu,
alex@...ti.fr,
samuel.holland@...ive.com
Cc: linux-doc@...r.kernel.org,
devicetree@...r.kernel.org,
linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org,
Cyan Yang <cyan.yang@...ive.com>
Subject: [PATCH 05/12] dt-bindings: riscv: Add xsfvfnrclipxfqf ISA extension description
Add "xsfvfnrclipxfqf" ISA extension which is provided by SiFive for
FP32-to-int8 ranged clip instructions support.
Signed-off-by: Cyan Yang <cyan.yang@...ive.com>
---
Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index d36e7c68d69a..be203df29eb8 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -675,6 +675,12 @@ properties:
See more details in
https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification
+ - const: xsfvfnrclipxfqf
+ description:
+ SiFive FP32-to-int8 Ranged Clip Instructions Extensions Specification.
+ See more details in
+ https://www.sifive.com/document-file/fp32-to-int8-ranged-clip-instructions
+
# T-HEAD
- const: xtheadvector
description:
--
2.39.5 (Apple Git-154)
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