linux-kernel - Re: [PATCH v2 15/15] drm: renesas: rz-du: mipi

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Message-ID: <CA+V-a8uyj0myd=At83X+=MnQqTdkpo3tyADgOPuTL_FjzPZD8g@mail.gmail.com>
Date: Fri, 18 Apr 2025 16:15:39 +0100
From: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To: Geert Uytterhoeven <geert@...ux-m68k.org>
Cc: Fabrizio Castro <fabrizio.castro.jz@...esas.com>, Andrzej Hajda <andrzej.hajda@...el.com>, 
	Neil Armstrong <neil.armstrong@...aro.org>, Robert Foss <rfoss@...nel.org>, 
	Laurent Pinchart <Laurent.pinchart@...asonboard.com>, Jonas Karlman <jonas@...boo.se>, 
	Jernej Skrabec <jernej.skrabec@...il.com>, David Airlie <airlied@...il.com>, 
	Simona Vetter <simona@...ll.ch>, Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>, 
	Maxime Ripard <mripard@...nel.org>, Thomas Zimmermann <tzimmermann@...e.de>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Biju Das <biju.das.jz@...renesas.com>, 
	Tomi Valkeinen <tomi.valkeinen+renesas@...asonboard.com>, 
	Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, 
	Philipp Zabel <p.zabel@...gutronix.de>, Magnus Damm <magnus.damm@...il.com>, 
	dri-devel@...ts.freedesktop.org, devicetree@...r.kernel.org, 
	linux-clk@...r.kernel.org, linux-renesas-soc@...r.kernel.org, 
	linux-kernel@...r.kernel.org, 
	Tommaso Merciai <tommaso.merciai.xr@...renesas.com>, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH v2 15/15] drm: renesas: rz-du: mipi_dsi: Add support for
 RZ/V2H(P) SoC

Hi Geert,

Thank you for the review.

On Wed, Apr 16, 2025 at 10:35 AM Geert Uytterhoeven
<geert@...ux-m68k.org> wrote:
>
> Hi Prabhakar, Fabrizio,
>
> On Tue, 8 Apr 2025 at 22:09, Prabhakar <prabhakar.csengg@...il.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> >
> > Add DSI support for Renesas RZ/V2H(P) SoC.
> >
> > Co-developed-by: Fabrizio Castro <fabrizio.castro.jz@...esas.com>
> > Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@...esas.com>
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
>
> Thanks for your patch!
>
> > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> > @@ -70,6 +80,18 @@ struct rzg2l_mipi_dsi {
> >         unsigned int num_data_lanes;
> >         unsigned int lanes;
> >         unsigned long mode_flags;
> > +
> > +       struct rzv2h_dsi_mode_calc mode_calc;
> > +       struct rzv2h_plldsi_parameters dsi_parameters;
> > +};
> > +
> > +static const struct rzv2h_plldsi_div_limits rzv2h_plldsi_div_limits = {
> > +       .m = { .min = 64, .max = 1023 },
>
> .max = 533?
>
> > +       .p = { .min = 1, .max = 4 },
> > +       .s = { .min = 0, .max = 5 },
>
> .max = 6?
>
> > +       .k = { .min = -32768, .max = 32767 },
> > +       .csdiv = { .min = 1, .max = 1 },
> > +       .fvco = { .min = 1050 * MEGA, .max = 2100 * MEGA }
> >  };
>
> Summarized: why do these values differ from the ones in the declaration
> macro RZV2H_CPG_PLL_DSI_LIMITS(), i.e. why can't you use the latter?
>
There is a divider inside the DSI IP which is almost similar to PLL in
the CPG. The divider limits for the DSI IP vary as compared to one in
the CPG IP.

Cheers,
Prabhakar