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Message-ID: <ebfd728a-7994-4fd4-9e58-1336fb5f9237@baylibre.com>
Date: Fri, 18 Apr 2025 11:15:37 -0500
From: David Lechner <dlechner@...libre.com>
To: Jonathan Cameron <jic23@...nel.org>,
 Angelo Dureghello <adureghello@...libre.com>
Cc: Lars-Peter Clausen <lars@...afoo.de>,
 Michael Hennerich <Michael.Hennerich@...log.com>,
 Nuno Sá <nuno.sa@...log.com>,
 Andy Shevchenko <andy@...nel.org>, Beniamin Bia <beniamin.bia@...log.com>,
 Jonathan Cameron <Jonathan.Cameron@...wei.com>, linux-iio@...r.kernel.org,
 linux-kernel@...r.kernel.org
Subject: Re: [PATCH] iio: adc: ad7606: fix serial register access

On 4/18/25 10:56 AM, Jonathan Cameron wrote:
> On Thu, 17 Apr 2025 23:42:51 +0200
> Angelo Dureghello <adureghello@...libre.com> wrote:
> 
>> From: Angelo Dureghello <adureghello@...libre.com>
>>
>> Fix register read/write routine as per datasheet.
>>
>> When reading multiple consecutive registers, only the first one is read
>> properly. This is due to missing chip select between first and second
>> 16bit transfer.
> In what sense of missing? Given code you mean missing being unselected
> briefly between transfers I think.
> 
> chip select itself is always set in current code and hence the 'missing'
> description had me confused!

Agree it would be better to describe this as missing the momentary chip select
deassert between the transfers.

Reviewed-by: David Lechner <dlechner@...libre.com>


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