linux-kernel - Re: [PATCH 2/7] arm64: dts: ti: k3-j7200-main: switch to 64-bit address space for PCIe1

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Message-ID: <8b707fbc-9d82-48d0-a227-366d4e83e8a7@ti.com>
Date: Sat, 19 Apr 2025 23:35:50 +0530
From: "Kumar, Udit" <u-kumar1@...com>
To: Siddharth Vadapalli <s-vadapalli@...com>, <nm@...com>, <vigneshr@...com>,
        <kristo@...nel.org>, <robh@...nel.org>, <krzk+dt@...nel.org>,
        <conor+dt@...nel.org>
CC: <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>, <srk@...com>,
        <u-kumar1@...com>
Subject: Re: [PATCH 2/7] arm64: dts: ti: k3-j7200-main: switch to 64-bit
 address space for PCIe1


On 4/17/2025 5:34 PM, Siddharth Vadapalli wrote:
> The PCIe0 instance of PCIe in J7200 SoC supports:
> 1. 128 MB address region in the 32-bit address space
> 2. 4 GB address region in the 64-bit address space
>
> The default configuration is that of a 128 MB address region in the
> 32-bit address space. While this might be sufficient for most use-cases,
> it is insufficient for supporting use-cases which require larger address
> spaces. Therefore, switch to using the 64-bit address space with a 4 GB
> address region.
>
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@...com>
> ---
>   arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 7 ++++---
>   1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> index 5ab510a0605f..e898dffdebbe 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> @@ -759,7 +759,7 @@ pcie1_rc: pcie@...0000 {
>   		reg = <0x00 0x02910000 0x00 0x1000>,
>   		      <0x00 0x02917000 0x00 0x400>,
>   		      <0x00 0x0d800000 0x00 0x00800000>,
> -		      <0x00 0x18000000 0x00 0x00001000>;
> +		      <0x41 0x00000000 0x00 0x00001000>;
>   		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
>   		interrupt-names = "link_state";
>   		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
> @@ -778,8 +778,9 @@ pcie1_rc: pcie@...0000 {
>   		device-id = <0xb00f>;
>   		msi-map = <0x0 &gic_its 0x0 0x10000>;
>   		dma-coherent;
> -		ranges = <0x01000000 0x0 0x18001000  0x00 0x18001000  0x0 0x0010000>,
> -			 <0x02000000 0x0 0x18011000  0x00 0x18011000  0x0 0x7fef000>;
> +		ranges = <0x01000000 0x00 0x00001000 0x41 0x00001000 0x00 0x00100000>, /* IO (1 MB) */
> +			 <0x02000000 0x00 0x00101000 0x41 0x00101000 0x00 0x08000000>, /* 32-bit Non-Prefetchable MEM (128 MB) */
> +			 <0x43000000 0x41 0x08101000 0x41 0x08101000 0x00 0xf7eff000>; /* 64-bit Prefetchable MEM (4 GB - (129 MB + 4 KB)) */

Sorry for novice question,

with this change,  How do you see  old EP working which supports 32 bit 
addressing,

or some translation is possible ?

0x43000000 0x41 0x08101000 0x41 0x08101000 0x00 0xf7eff000>

to

0x63000000 0x00 0x08101000 0x41 0x08101000 0x00 0xf7eff000>


>   		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
>   		status = "disabled";
>   	};