linux-kernel - Re: [PATCH 4/9] dt-bindings: interrupt-controller: add Andes machine-level software interrupt controller

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Message-ID: <aAY30QwzG6/7RWhE@atctrx.andestech.com>
Date: Mon, 21 Apr 2025 20:19:29 +0800
From: Ben Zong-You Xie <ben717@...estech.com>
To: Rob Herring <robh@...nel.org>
CC: <devicetree@...r.kernel.org>, <linux-riscv@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>, <paul.walmsley@...ive.com>,
        <palmer@...belt.com>, <aou@...s.berkeley.edu>, <alex@...ti.fr>,
        <krzk+dt@...nel.org>, <conor+dt@...nel.org>, <tglx@...utronix.de>,
        <daniel.lezcano@...aro.org>, <prabhakar.mahadev-lad.rj@...renesas.com>,
        <tim609@...estech.com>
Subject: Re: [PATCH 4/9] dt-bindings: interrupt-controller: add Andes
 machine-level software interrupt controller

On Mon, Apr 07, 2025 at 09:17:08AM -0500, Rob Herring wrote:
> [EXTERNAL MAIL]
> 
> On Mon, Apr 07, 2025 at 06:49:32PM +0800, Ben Zong-You Xie wrote:
> > Add the DT binding documentation for Andes machine-level software
> > interrupt controller.
> >
> > In the Andes platform such as QiLai SoC, the PLIC module is instantiated a
> > second time with all interrupt sources tied to zero as the software
> > interrupt controller (PLICSW). PLICSW can generate machine-level software
> > interrupts through programming its registers.
> >
> > Signed-off-by: Ben Zong-You Xie <ben717@...estech.com>
> > ---
> >  .../andestech,plicsw.yaml                     | 48 +++++++++++++++++++
> >  MAINTAINERS                                   |  1 +
> >  2 files changed, 49 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml b/Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml
> > new file mode 100644
> > index 000000000000..5432fcfd95ed
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml
> > @@ -0,0 +1,48 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/interrupt-controller/andestech,plicsw.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Andes machine-level software interrupt controller
> > +
> > +description:
> > +  In the Andes platform such as QiLai SoC, the PLIC module is instantiated a
> > +  second time with all interrupt sources tied to zero as the software interrupt
> > +  controller (PLIC_SW). PLIC_SW can generate machine-level software interrupts
> > +  through programming its registers.
> > +
> > +maintainers:
> > +  - Ben Zong-You Xie <ben717@...estech.com>
> > +
> > +properties:
> > +  compatible:
> > +    items:
> > +      - enum:
> > +          - andestech,qilai-plicsw
> > +      - const: andestech,plicsw
> 
> Drop the fallback. If you have another implementation that's compatible,
> then andestech,qilai-plicsw will be the fallback.
>

Hi Rob,

Maybe this is a stupid question, but I don't understand the reason for
dropping the fallback. I follow the same logic in commit 1267d9831171
(dt-bindings: interrupt-controller: sifive,plic: Document Renesas RZ/Five
SoC). Thus, I think if there is a new SoC also equipped with Andes
PLIC-SW (NCEPLIC100-SW), the SoC vendor can simply add a new compatible
string under the enum.

Also, I will rename andestech,plisw to andestech,nceplic100-sw if the
fallback string is not dropped.

Thanks,
Ben

> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  interrupts-extended:
> > +    minItems: 1
> > +    maxItems: 15872
> > +
> > +additionalProperties: false
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - interrupts-extended
> > +
> > +examples:
> > +  - |
> > +    interrupt-controller@...000 {
> > +      compatible = "andestech,qilai-plicsw", "andestech,plicsw";
> > +      reg = <0x400000 0x400000>;
> > +      interrupts-extended = <&cpu0intc 3>,
> > +                            <&cpu1intc 3>,
> > +                            <&cpu2intc 3>,
> > +                            <&cpu3intc 3>;
> > +    };
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index a0ccac1cca29..645d7137cb07 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -20728,6 +20728,7 @@ F:    include/linux/irqchip/riscv-imsic.h
> >  RISC-V ANDES SoC Support
> >  M:   Ben Zong-You Xie <ben717@...estech.com>
> >  S:   Maintained
> > +F:   Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml
> >  F:   Documentation/devicetree/bindings/riscv/andes.yaml
> >
> >  RISC-V ARCHITECTURE
> > --
> > 2.34.1
> >