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Message-Id: <20250421142441.395849-1-alexghiti@rivosinc.com>
Date: Mon, 21 Apr 2025 16:24:37 +0200
From: Alexandre Ghiti <alexghiti@...osinc.com>
To: Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Alexandre Ghiti <alex@...ti.fr>,
linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org
Cc: Alexandre Ghiti <alexghiti@...osinc.com>
Subject: [PATCH v3 0/4] riscv: Add Zicbop & prefetchw support
I found this lost series developed by Guo so here is a respin with the
comments on v2 applied.
This patch series adds Zicbop support and then enables the Linux
prefetch features.
Changelog:
V3:
- Fix typo (Drew)
- Split first patch (Drew)
- Ensure that the bits [0:4] of the prefetch insns are zeroed
- Move PREFETCHW_ASM out of ifdef (Guo)
- Remove CBO_ prefix for prefetching insn
- Add prefetch (Drew)
V2: https://lore.kernel.org/linux-riscv/20231231082955.16516-1-guoren@kernel.org/
- Separate from the qspinlock series
- Optimize coding convention with last review advice
- Add DEFINE_INSN_S type in insn-def.h
- Add CBO_PREFETCH_I/R/W
V1:
https://lore.kernel.org/linux-riscv/20230910082911.3378782-4-guoren@kernel.org/
Alexandre Ghiti (2):
riscv: Introduce Zicbop instructions
riscv: Add support for Zicbop
Guo Ren (2):
riscv: Add ARCH_HAS_PREFETCH[W] support with Zicbop
riscv: xchg: Prefetch the destination word for sc.w
arch/riscv/Kconfig | 15 +++++++
arch/riscv/include/asm/barrier.h | 5 ---
arch/riscv/include/asm/cacheflush.h | 1 +
arch/riscv/include/asm/cmpxchg.h | 4 +-
arch/riscv/include/asm/hwcap.h | 1 +
arch/riscv/include/asm/insn-def.h | 66 +++++++++++++++++++++++++++++
arch/riscv/include/asm/processor.h | 25 ++++++++++-
arch/riscv/kernel/cpufeature.c | 21 +++++++++
arch/riscv/mm/cacheflush.c | 14 ++++--
9 files changed, 142 insertions(+), 10 deletions(-)
--
2.39.2
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