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Message-ID: <20250422120042.3746004-1-s-vadapalli@ti.com>
Date: Tue, 22 Apr 2025 17:30:35 +0530
From: Siddharth Vadapalli <s-vadapalli@...com>
To: <nm@...com>, <vigneshr@...com>, <kristo@...nel.org>, <robh@...nel.org>,
<krzk+dt@...nel.org>, <conor+dt@...nel.org>, <u-kumar1@...com>
CC: <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>, <srk@...com>,
<s-vadapalli@...com>
Subject: [PATCH v2 0/7] AM64 and J7X DT: Enable PCIe 64-bit Address Space
Hello,
The Cadence PCIe Controllers in TI's K3 SoCs namely:
AM64, J7200, J721E, J721S2 (AM68), J722S, J742S2 and J784S4 (AM69)
support two address regions:
1. 128 MB address region in the 32-bit address space
2. 4 GB address region in the 64-bit address space
Currently, the 128 MB region in the 32-bit address space is enabled in
the device-tree. This might be suitable for most of the use-cases, but
for those use-cases requiring larger address regions than 128 MB it is
necessary to switch to the 64-bit address space with the 4 GB address
region. This series implements the corresponding device-tree changes to
support the 4 GB address region as the default configuration. Existing
use-cases should continue to work without any regression.
Series is based on linux-next tagged next-20250417.
Link to v1 series:
https://lore.kernel.org/r/20250417120407.2646929-1-s-vadapalli@ti.com/
Changes since v1 series:
- Fixed the 'ranges' in k3-j721e.dtsi which is the third patch of the
series to set the size as 4 GB instead of the incorrect value of 128 MB.
- Based on Udit's feedback and offline discussion as described at:
https://lore.kernel.org/r/7f6ea98c-df6d-4c94-8f42-76cc8306b6c4@ti.com/
the address region of 4 GB is split as:
0. 4 KB ECAM
1. 1 MB IO
2. (4 GB - 1 MB - 4 KB) 32-bit Non-Prefetchable MEM
instead of the previous split of:
0. 4 KB ECAM
1. 1 MB IO
2. 128 MB 32-bit Non-Prefetchable MEM
3. (4 GB - 129 MB - 4 KB) 64-bit Prefetchable MEM
Series has been tested on AM642-EVM, J7200-EVM, J721E-EVM, J721S2-EVM,
J722S-EVM and J784S4-EVM using an NVMe SSD connected to the PCIe
Connector on the EVMs.
Test Logs:
1. AM642-EVM PCIe0
https://gist.github.com/Siddharth-Vadapalli-at-TI/5d1814ee2e0857dac0ac08a6cf8759da
2. J7200-EVM PCIe1
https://gist.github.com/Siddharth-Vadapalli-at-TI/9927faab7615b9c1c101854a213f30f5
3. J721E-EVM PCIe0
https://gist.github.com/Siddharth-Vadapalli-at-TI/e6545e31f45077fe59c896f8875bf1b9
4. J721E-EVM PCIe1
https://gist.github.com/Siddharth-Vadapalli-at-TI/5c0b64f339f89139797d8346c40b1ee9
5. J721S2-EVM PCIe1
https://gist.github.com/Siddharth-Vadapalli-at-TI/67b03c441d53ef0d27837e615371efbd
6. J722S-EVM PCIe0
https://gist.github.com/Siddharth-Vadapalli-at-TI/7625f47b57d45aada4c125ac4f60ebd6
7. J784S4-EVM PCIe0
https://gist.github.com/Siddharth-Vadapalli-at-TI/edf2af424fc7d5905832d536a1171a1a
Regards,
Siddharth.
Siddharth Vadapalli (7):
arm64: dts: ti: k3-am64-main: switch to 64-bit address space for PCIe0
arm64: dts: ti: k3-j7200-main: switch to 64-bit address space for
PCIe1
arm64: dts: ti: k3-j721e: add ranges for PCIe0 DAT1 and PCIe1 DAT1
arm64: dts: ti: k3-j721e-main: switch to 64-bit address space for
PCIe0 and PCIe1
arm64: dts: ti: k3-j721s2-main: switch to 64-bit address space for
PCIe1
arm64: dts: ti: k3-j722s-main: switch to 64-bit address space for
PCIe0
arm64: dts: ti: k3-j784s4-j742s2-main-common: switch to 64-bit address
space for PCIe0 and PCIe1
arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 6 +++---
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 6 +++---
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 12 ++++++------
arch/arm64/boot/dts/ti/k3-j721e.dtsi | 2 ++
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 6 +++---
arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 6 +++---
.../boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi | 12 ++++++------
7 files changed, 26 insertions(+), 24 deletions(-)
--
2.34.1
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