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Message-ID: <28e3f91f-a786-4ec6-ae70-bd92c11be81a@collabora.com>
Date: Tue, 22 Apr 2025 16:37:50 +0200
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
To: Jianhua Lin <jianhua.lin@...iatek.com>, mchehab@...nel.org,
matthias.bgg@...il.com
Cc: linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org,
Project_Global_Chrome_Upstream_Group@...iatek.com
Subject: Re: [PATCH 1/1] media: mediatek: jpeg: fix buffer alignment
Il 18/04/25 05:25, Jianhua Lin ha scritto:
> From: "jianhua.lin" <jianhua.lin@...iatek.com>
>
> The JPEG encoder image stride register must be MCU aligned.
> For YUV422, it's 32-byte aligned, and for YUV420, it's
> 16-byte aligned.
>
> The minimal DCT block size is 8x8, so the vertical buffer
> alignment for YUV422 is 8-byte aligned, and for YUV420,
> it's 16-byte aligned.
>
> Signed-off-by: jianhua.lin <jianhua.lin@...iatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
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