linux-kernel - Re: [PATCH] clk: rockchip: rk3568: Add PLL rate for 33.3MHz

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Message-ID: <CA+E=qVc7tG7LXA86c_Urp0B3a+Oo6+ssZ_vDp8hvDDW-n1M6cA@mail.gmail.com>
Date: Tue, 22 Apr 2025 13:25:40 -0700
From: Vasily Khoruzhick <anarsoul@...il.com>
To: Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, 
	Heiko Stuebner <heiko@...ech.de>, linux-clk@...r.kernel.org, 
	linux-arm-kernel@...ts.infradead.org, linux-rockchip@...ts.infradead.org, 
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH] clk: rockchip: rk3568: Add PLL rate for 33.3MHz

On Tue, Mar 18, 2025 at 11:19 AM Vasily Khoruzhick <anarsoul@...il.com> wrote:
>
> Add PLL rate for 33.3 MHz to allow BTT HDMI5 screen to run at its native
> mode of 800x480

Ping

> Signed-off-by: Vasily Khoruzhick <anarsoul@...il.com>
> ---
>  drivers/clk/rockchip/clk-rk3568.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c
> index 53d10b1c627b..1c73e18a9862 100644
> --- a/drivers/clk/rockchip/clk-rk3568.c
> +++ b/drivers/clk/rockchip/clk-rk3568.c
> @@ -89,6 +89,7 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
>         RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
>         RK3036_PLL_RATE(78750000, 4, 315, 6, 4, 1, 0),
>         RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0),
> +       RK3036_PLL_RATE(33300000, 4, 111, 5, 4, 1, 0),
>         { /* sentinel */ },
>  };
>
> --
> 2.49.0
>