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Message-ID: <b858e1a3-7bad-4e23-bd95-d409a29195ad@zohomail.com>
Date: Tue, 22 Apr 2025 12:18:26 +0800
From: Xukai Wang <kingxukai@...omail.com>
To: Chen Wang <unicorn_wang@...look.com>,
Michael Turquette <mturquette@...libre.com>, Stephen Boyd
<sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
<conor+dt@...nel.org>, Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>,
Conor Dooley <conor@...nel.org>
Cc: linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org,
Samuel Holland <samuel.holland@...ive.com>,
Troy Mitchell <TroyMitchell988@...il.com>,
Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Subject: Re: [PATCH v6 1/3] dt-bindings: clock: Add bindings for Canaan K230
clock controller
On 2025/4/21 18:47, Chen Wang wrote:
>
> On 2025/4/15 22:25, Xukai Wang wrote:
>> This patch adds the Device Tree binding for the clock controller
>> on Canaan k230. The binding defines the new clocks available and
>> the required properties to configure them correctly.
>>
>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
>> Signed-off-by: Xukai Wang <kingxukai@...omail.com>
>> ---
>> .../devicetree/bindings/clock/canaan,k230-clk.yaml | 43 ++++++++++++++
>> include/dt-bindings/clock/canaan,k230-clk.h | 69
>> ++++++++++++++++++++++
>> 2 files changed, 112 insertions(+)
>>
>> diff --git
>> a/Documentation/devicetree/bindings/clock/canaan,k230-clk.yaml
>> b/Documentation/devicetree/bindings/clock/canaan,k230-clk.yaml
>> new file mode 100644
>> index
>> 0000000000000000000000000000000000000000..d7220fa30e4699a68fa5279c04abc63c1905fa4a
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/canaan,k230-clk.yaml
>> @@ -0,0 +1,43 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/canaan,k230-clk.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Canaan Kendryte K230 Clock
>> +
>> +maintainers:
>> + - Xukai Wang <kingxukai@...omail.com>
>> +
>> +properties:
>> + compatible:
>> + const: canaan,k230-clk
>> +
>> + reg:
>> + items:
>> + - description: PLL control registers.
>> + - description: Sysclk control registers.
>> +
>> + clocks:
>> + maxItems: 1
>> +
>> + '#clock-cells':
>> + const: 1
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - clocks
>> + - '#clock-cells'
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + clock-controller@...02000 {
>> + compatible = "canaan,k230-clk";
>> + reg = <0x91102000 0x1000>,
>
> Note that when actually writing DTS, the PLL-related register range is
> not so large (0x1000). Otherwise, the BOOT-related registers may be
> overwritten.
>
I get the point. Although I won't modify other registers unrelated to
PLL, I will still refine the mapped areas(0x40 size).
>
>> + <0x91100000 0x1000>;
>> + clocks = <&osc24m>;
>> + #clock-cells = <1>;
>> + };
>> diff --git a/include/dt-bindings/clock/canaan,k230-clk.h
>> b/include/dt-bindings/clock/canaan,k230-clk.h
>> new file mode 100644
>> index
>> 0000000000000000000000000000000000000000..41edb13ea04bffaa1ddd1d1af87ae3406b688332
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/canaan,k230-clk.h
>> @@ -0,0 +1,69 @@
>> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
>> +/*
>> + * Kendryte Canaan K230 Clock Drivers
>> + *
>> + * Author: Xukai Wang <kingxukai@...omail.com>
>> + */
>> +
>> +#ifndef CLOCK_K230_CLK_H
>> +#define CLOCK_K230_CLK_H
>> +
>> +/* Kendryte K230 SoC clock identifiers (arbitrary values). */
>> +#define K230_CPU0_SRC 0
>> +#define K230_CPU0_ACLK 1
>> +#define K230_CPU0_PLIC 2
>> +#define K230_CPU0_NOC_DDRCP4 3
>> +#define K230_CPU0_PCLK 4
>> +#define K230_PMU_PCLK 5
>> +#define K230_HS_HCLK_HIGH_SRC 6
>> +#define K230_HS_HCLK_HIGH_GATE 7
>> +#define K230_HS_HCLK_SRC 8
>> +#define K230_HS_SD0_HS_AHB_GAT 9
>> +#define K230_HS_SD1_HS_AHB_GAT 10
>> +#define K230_HS_SSI1_HS_AHB_GA 11
>> +#define K230_HS_SSI2_HS_AHB_GA 12
>> +#define K230_HS_USB0_HS_AHB_GA 13
>> +#define K230_HS_USB1_HS_AHB_GA 14
>> +#define K230_HS_SSI0_AXI15 15
>> +#define K230_HS_SSI1 16
>> +#define K230_HS_SSI2 17
>> +#define K230_HS_QSPI_AXI_SRC 18
>> +#define K230_HS_SSI1_ACLK_GATE 19
>> +#define K230_HS_SSI2_ACLK_GATE 20
>> +#define K230_HS_SD_CARD_SRC 21
>> +#define K230_HS_SD0_CARD_TX 22
>> +#define K230_HS_SD1_CARD_TX 23
>> +#define K230_HS_SD_AXI_SRC 24
>> +#define K230_HS_SD0_AXI_GATE 25
>> +#define K230_HS_SD1_AXI_GATE 26
>> +#define K230_HS_SD0_BASE_GATE 27
>> +#define K230_HS_SD1_BASE_GATE 28
>> +#define K230_HS_OSPI_SRC 29
>> +#define K230_HS_USB_REF_50M 30
>> +#define K230_HS_SD_TIMER_SRC 31
>> +#define K230_HS_SD0_TIMER_GATE 32
>> +#define K230_HS_SD1_TIMER_GATE 33
>> +#define K230_HS_USB0_REFERENCE 34
>> +#define K230_HS_USB1_REFERENCE 35
>> +#define K230_LS_APB_SRC 36
>> +#define K230_LS_UART0_APB 37
>> +#define K230_LS_UART1_APB 38
>> +#define K230_LS_UART2_APB 39
>> +#define K230_LS_UART3_APB 40
>> +#define K230_LS_UART4_APB 41
>> +#define K230_LS_I2C0_APB 42
>> +#define K230_LS_I2C1_APB 43
>> +#define K230_LS_I2C2_APB 44
>> +#define K230_LS_I2C3_APB 45
>> +#define K230_LS_GPIO_APB 46
>> +#define K230_LS_PWM_APB 47
>> +#define K230_LS_UART0 48
>> +#define K230_LS_UART1 49
>> +#define K230_LS_UART2 50
>> +#define K230_LS_UART3 51
>> +#define K230_LS_UART4 52
>> +#define K230_SHRM_AXI_SRC 53
>> +#define K230_SHRM_SDMA_AXI_GATE 54
>> +#define K230_SHRM_PDMA_AXI_GATE 55
>> +
>
> It seems that some clks are missing, such as the timer-related clocks.
> Please try to fill them in. There is no need to submit another patch
> for this.
OK, I'll complete the rest clock next version.
>
> Thanks,
>
> Chen
>
>> +#endif /* CLOCK_K230_CLK_H */
>>
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