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Message-ID: <CA+V-a8vMLUnZiJZjj0mu_DGSmZ5F_a0_U_SpmEaVxqL+ZqGrOA@mail.gmail.com>
Date: Tue, 22 Apr 2025 09:32:35 +0100
From: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To: Biju Das <biju.das.jz@...renesas.com>
Cc: Andrzej Hajda <andrzej.hajda@...el.com>, Neil Armstrong <neil.armstrong@...aro.org>,
Robert Foss <rfoss@...nel.org>, "laurent.pinchart" <laurent.pinchart@...asonboard.com>,
Jonas Karlman <jonas@...boo.se>, Jernej Skrabec <jernej.skrabec@...il.com>,
David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>, Maxime Ripard <mripard@...nel.org>,
Thomas Zimmermann <tzimmermann@...e.de>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
Geert Uytterhoeven <geert+renesas@...der.be>, Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Philipp Zabel <p.zabel@...gutronix.de>,
Magnus Damm <magnus.damm@...il.com>,
"dri-devel@...ts.freedesktop.org" <dri-devel@...ts.freedesktop.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-renesas-soc@...r.kernel.org" <linux-renesas-soc@...r.kernel.org>,
"linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>,
Fabrizio Castro <fabrizio.castro.jz@...esas.com>,
Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH v3 15/15] drm: renesas: rz-du: mipi_dsi: Add support for
RZ/V2H(P) SoC
Hi Biju,
Thank you for the review.
On Sat, Apr 19, 2025 at 8:28 AM Biju Das <biju.das.jz@...renesas.com> wrote:
>
> Hi Prabhakar,
>
> Thanks for the patch.
>
> > -----Original Message-----
> > From: Prabhakar <prabhakar.csengg@...il.com>
> > Sent: 18 April 2025 19:47
> > Subject: [PATCH v3 15/15] drm: renesas: rz-du: mipi_dsi: Add support for RZ/V2H(P) SoC
> >
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> >
> > Add DSI support for Renesas RZ/V2H(P) SoC.
> >
> > Co-developed-by: Fabrizio Castro <fabrizio.castro.jz@...esas.com>
> > Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@...esas.com>
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> > ---
> > v2->v3:
> > - Simplifed V2H DSI timings array to save space
> > - Switched to use fsleep() instead of udelay()
> >
> > v1->v2:
> > - Dropped unused macros
> > - Added missing LPCLK flag to rzvv2h info
> > ---
> > .../gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 344 ++++++++++++++++++
> > .../drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h | 34 ++
> > 2 files changed, 378 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/drm/renesas/rz-
> > du/rzg2l_mipi_dsi.c
> > index 133a8f306d47..a957b6c5f28d 100644
> > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> > @@ -5,6 +5,7 @@
> > * Copyright (C) 2022 Renesas Electronics Corporation
> > */
> > #include <linux/clk.h>
> > +#include <linux/clk/renesas-rzv2h-dsi.h>
> > #include <linux/delay.h>
> > #include <linux/io.h>
> > #include <linux/iopoll.h>
> > @@ -32,6 +33,9 @@
> > #define RZ_MIPI_DSI_FEATURE_16BPP BIT(1)
> > #define RZ_MIPI_DSI_FEATURE_LPCLK BIT(2)
> >
> > +#define RZV2H_MIPI_DPHY_FOUT_MIN_IN_MEGA (80 * MEGA)
> > +#define RZV2H_MIPI_DPHY_FOUT_MAX_IN_MEGA (1500 * MEGA)
> > +
> > struct rzg2l_mipi_dsi;
> >
> > struct rzg2l_mipi_dsi_hw_info {
> > @@ -42,6 +46,7 @@ struct rzg2l_mipi_dsi_hw_info {
> > u64 *hsfreq_millihz);
> > unsigned int (*dphy_mode_clk_check)(struct rzg2l_mipi_dsi *dsi,
> > unsigned long mode_freq);
> > + const struct rzv2h_pll_div_limits *cpg_dsi_limits;
> > u32 phy_reg_offset;
> > u32 link_reg_offset;
> > unsigned long max_dclk;
> > @@ -49,6 +54,11 @@ struct rzg2l_mipi_dsi_hw_info {
> > u8 features;
> > };
> >
> > +struct rzv2h_dsi_mode_calc {
> > + unsigned long mode_freq;
> > + u64 mode_freq_hz;
> > +};
> > +
> > struct rzg2l_mipi_dsi {
> > struct device *dev;
> > void __iomem *mmio;
> > @@ -70,6 +80,18 @@ struct rzg2l_mipi_dsi {
> > unsigned int num_data_lanes;
> > unsigned int lanes;
> > unsigned long mode_flags;
> > +
> > + struct rzv2h_dsi_mode_calc mode_calc;
> > + struct rzv2h_plldsi_parameters dsi_parameters; };
> > +
> > +static const struct rzv2h_pll_div_limits rzv2h_plldsi_div_limits = {
> > + .fvco = { .min = 1050 * MEGA, .max = 2100 * MEGA },
> > + .m = { .min = 64, .max = 1023 },
> > + .p = { .min = 1, .max = 4 },
> > + .s = { .min = 0, .max = 5 },
> > + .k = { .min = -32768, .max = 32767 },
> > + .csdiv = { .min = 1, .max = 1 },
> > };
> >
> > static inline struct rzg2l_mipi_dsi *
> > @@ -186,6 +208,155 @@ static const struct rzg2l_mipi_dsi_timings rzg2l_mipi_dsi_global_timings[] = {
> > },
> > };
> >
> > +struct rzv2h_mipi_dsi_timings {
> > + const u8 *hsfreq;
> > + u8 len;
> > + u8 start_index;
> > +};
> > +
> > +enum {
> > + TCLKPRPRCTL,
> > + TCLKZEROCTL,
> > + TCLKPOSTCTL,
> > + TCLKTRAILCTL,
> > + THSPRPRCTL,
> > + THSZEROCTL,
> > + THSTRAILCTL,
> > + TLPXCTL,
> > + THSEXITCTL,
> > +};
> > +
> > +static const u8 tclkprprctl[] = {
> > + 15, 26, 37, 47, 58, 69, 79, 90, 101, 111, 122, 133, 143, 150, };
> > +
> > +static const u8 tclkzeroctl[] = {
> > + 9, 11, 13, 15, 18, 21, 23, 24, 25, 27, 29, 31, 34, 36, 38,
> > + 41, 43, 45, 47, 50, 52, 54, 57, 59, 61, 63, 66, 68, 70, 73,
> > + 75, 77, 79, 82, 84, 86, 89, 91, 93, 95, 98, 100, 102, 105,
> > + 107, 109, 111, 114, 116, 118, 121, 123, 125, 127, 130, 132,
> > + 134, 137, 139, 141, 143, 146, 148, 150, };
> > +
> > +static const u8 tclkpostctl[] = {
> > + 8, 21, 34, 48, 61, 74, 88, 101, 114, 128, 141, 150, };
> > +
> > +static const u8 tclktrailctl[] = {
> > + 14, 25, 37, 48, 59, 71, 82, 94, 105, 117, 128, 139, 150, };
> > +
> > +static const u8 thsprprctl[] = {
> > + 11, 19, 29, 40, 50, 61, 72, 82, 93, 103, 114, 125, 135, 146, 150, };
> > +
> > +static const u8 thszeroctl[] = {
> > + 18, 24, 29, 35, 40, 46, 51, 57, 62, 68, 73, 79, 84, 90,
> > + 95, 101, 106, 112, 117, 123, 128, 134, 139, 145, 150, };
> > +
> > +static const u8 thstrailctl[] = {
> > + 10, 21, 32, 42, 53, 64, 75, 85, 96, 107, 118, 128, 139, 150, };
> > +
> > +static const u8 tlpxctl[] = {
> > + 13, 26, 39, 53, 66, 79, 93, 106, 119, 133, 146, 150,
> > +};
> > +
> > +static const u8 thsexitctl[] = {
> > + 15, 23, 31, 39, 47, 55, 63, 71, 79, 87,
> > + 95, 103, 111, 119, 127, 135, 143, 150, };
> > +
> > +static const struct rzv2h_mipi_dsi_timings rzv2h_dsi_timings_tables[] = {
> > + [TCLKPRPRCTL] = {
> > + .hsfreq = tclkprprctl,
> > + .len = ARRAY_SIZE(tclkprprctl),
> > + .start_index = 0,
> > + },
> > + [TCLKZEROCTL] = {
> > + .hsfreq = tclkzeroctl,
> > + .len = ARRAY_SIZE(tclkzeroctl),
> > + .start_index = 2,
> > + },
> > + [TCLKPOSTCTL] = {
> > + .hsfreq = tclkpostctl,
> > + .len = ARRAY_SIZE(tclkpostctl),
> > + .start_index = 6,
> > + },
> > + [TCLKTRAILCTL] = {
> > + .hsfreq = tclktrailctl,
> > + .len = ARRAY_SIZE(tclktrailctl),
> > + .start_index = 1,
> > + },
> > + [THSPRPRCTL] = {
> > + .hsfreq = thsprprctl,
> > + .len = ARRAY_SIZE(thsprprctl),
> > + .start_index = 0,
> > + },
> > + [THSZEROCTL] = {
> > + .hsfreq = thszeroctl,
> > + .len = ARRAY_SIZE(thszeroctl),
> > + .start_index = 0,
> > + },
> > + [THSTRAILCTL] = {
> > + .hsfreq = thstrailctl,
> > + .len = ARRAY_SIZE(thstrailctl),
> > + .start_index = 3,
> > + },
> > + [TLPXCTL] = {
> > + .hsfreq = tlpxctl,
> > + .len = ARRAY_SIZE(tlpxctl),
> > + .start_index = 0,
> > + },
> > + [THSEXITCTL] = {
> > + .hsfreq = thsexitctl,
> > + .len = ARRAY_SIZE(thsexitctl),
> > + .start_index = 1,
> > + },
> > +};
> > +
> > +static u16 rzv2h_dphy_find_ulpsexit(unsigned long freq) {
> > + const unsigned long hsfreq[] = {
>
> Please don't populate the read-only const array offsets on the stack
> but instead make it static, see [1] and [2]
>
Ok, I'll make it static in the next version.
> [1]
> https://lkml.iu.edu/2201.1/00608.html
> [2]
> https://patchwork.ozlabs.org/project/intel-wired-lan/patch/20250317144606.478431-1-colin.i.king@gmail.com/
>
Cheers,
Prabhakar
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