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Message-ID: <f5d40648-50a0-4f7b-a8ef-62eab26364dc@rivosinc.com>
Date: Tue, 22 Apr 2025 11:14:26 +0200
From: Clément Léger <cleger@...osinc.com>
To: Alexandre Ghiti <alexghiti@...osinc.com>,
Paul Walmsley <paul.walmsley@...ive.com>, Palmer Dabbelt
<palmer@...belt.com>, Alexandre Ghiti <alex@...ti.fr>,
Anup Patel <anup@...infault.org>, Atish Patra <atishp@...shpatra.org>,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
kvm@...r.kernel.org, kvm-riscv@...ts.infradead.org
Subject: Re: [PATCH 2/3] riscv: Strengthen duplicate and inconsistent
definition of RV_X()
On 22/04/2025 10:25, Alexandre Ghiti wrote:
> RV_X() macro is defined in two different ways which is error prone.
>
> So harmonize its first definition and add another macro RV_X_mask() for
> the second one.
>
> Signed-off-by: Alexandre Ghiti <alexghiti@...osinc.com>
> ---
> arch/riscv/include/asm/insn.h | 39 ++++++++++++++--------------
> arch/riscv/kernel/elf_kexec.c | 1 -
> arch/riscv/kernel/traps_misaligned.c | 1 -
> arch/riscv/kvm/vcpu_insn.c | 1 -
> 4 files changed, 20 insertions(+), 22 deletions(-)
>
> diff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h
> index 2a589a58b291..4063ca35be9b 100644
> --- a/arch/riscv/include/asm/insn.h
> +++ b/arch/riscv/include/asm/insn.h
> @@ -288,43 +288,44 @@ static __always_inline bool riscv_insn_is_c_jalr(u32 code)
>
> #define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))
> #define RVC_IMM_SIGN(x) (-(((x) >> 12) & 1))
> -#define RV_X(X, s, mask) (((X) >> (s)) & (mask))
> -#define RVC_X(X, s, mask) RV_X(X, s, mask)
> +#define RV_X(X, s, n) (((X) >> (s)) & ((1 << (n)) - 1))
> +#define RV_X_mask(X, s, mask) (((X) >> (s)) & (mask))
> +#define RVC_X(X, s, mask) RV_X_mask(X, s, mask)
Hi Alex,
I think RV_X() could be defined using RV_X_mask() as well:
#define RV_X(X, s, n) RV_X_mask(X, s, ((1 << (n)) - 1))
Thanks,
Clément
>
> #define RV_EXTRACT_RS1_REG(x) \
> ({typeof(x) x_ = (x); \
> - (RV_X(x_, RVG_RS1_OPOFF, RVG_RS1_MASK)); })
> + (RV_X_mask(x_, RVG_RS1_OPOFF, RVG_RS1_MASK)); })
>
> #define RV_EXTRACT_RD_REG(x) \
> ({typeof(x) x_ = (x); \
> - (RV_X(x_, RVG_RD_OPOFF, RVG_RD_MASK)); })
> + (RV_X_mask(x_, RVG_RD_OPOFF, RVG_RD_MASK)); })
>
> #define RV_EXTRACT_UTYPE_IMM(x) \
> ({typeof(x) x_ = (x); \
> - (RV_X(x_, RV_U_IMM_31_12_OPOFF, RV_U_IMM_31_12_MASK)); })
> + (RV_X_mask(x_, RV_U_IMM_31_12_OPOFF, RV_U_IMM_31_12_MASK)); })
>
> #define RV_EXTRACT_JTYPE_IMM(x) \
> ({typeof(x) x_ = (x); \
> - (RV_X(x_, RV_J_IMM_10_1_OPOFF, RV_J_IMM_10_1_MASK) << RV_J_IMM_10_1_OFF) | \
> - (RV_X(x_, RV_J_IMM_11_OPOFF, RV_J_IMM_11_MASK) << RV_J_IMM_11_OFF) | \
> - (RV_X(x_, RV_J_IMM_19_12_OPOFF, RV_J_IMM_19_12_MASK) << RV_J_IMM_19_12_OFF) | \
> + (RV_X_mask(x_, RV_J_IMM_10_1_OPOFF, RV_J_IMM_10_1_MASK) << RV_J_IMM_10_1_OFF) | \
> + (RV_X_mask(x_, RV_J_IMM_11_OPOFF, RV_J_IMM_11_MASK) << RV_J_IMM_11_OFF) | \
> + (RV_X_mask(x_, RV_J_IMM_19_12_OPOFF, RV_J_IMM_19_12_MASK) << RV_J_IMM_19_12_OFF) | \
> (RV_IMM_SIGN(x_) << RV_J_IMM_SIGN_OFF); })
>
> #define RV_EXTRACT_ITYPE_IMM(x) \
> ({typeof(x) x_ = (x); \
> - (RV_X(x_, RV_I_IMM_11_0_OPOFF, RV_I_IMM_11_0_MASK)) | \
> + (RV_X_mask(x_, RV_I_IMM_11_0_OPOFF, RV_I_IMM_11_0_MASK)) | \
> (RV_IMM_SIGN(x_) << RV_I_IMM_SIGN_OFF); })
>
> #define RV_EXTRACT_BTYPE_IMM(x) \
> ({typeof(x) x_ = (x); \
> - (RV_X(x_, RV_B_IMM_4_1_OPOFF, RV_B_IMM_4_1_MASK) << RV_B_IMM_4_1_OFF) | \
> - (RV_X(x_, RV_B_IMM_10_5_OPOFF, RV_B_IMM_10_5_MASK) << RV_B_IMM_10_5_OFF) | \
> - (RV_X(x_, RV_B_IMM_11_OPOFF, RV_B_IMM_11_MASK) << RV_B_IMM_11_OFF) | \
> + (RV_X_mask(x_, RV_B_IMM_4_1_OPOFF, RV_B_IMM_4_1_MASK) << RV_B_IMM_4_1_OFF) | \
> + (RV_X_mask(x_, RV_B_IMM_10_5_OPOFF, RV_B_IMM_10_5_MASK) << RV_B_IMM_10_5_OFF) | \
> + (RV_X_mask(x_, RV_B_IMM_11_OPOFF, RV_B_IMM_11_MASK) << RV_B_IMM_11_OFF) | \
> (RV_IMM_SIGN(x_) << RV_B_IMM_SIGN_OFF); })
>
> #define RVC_EXTRACT_C2_RS1_REG(x) \
> ({typeof(x) x_ = (x); \
> - (RV_X(x_, RVC_C2_RS1_OPOFF, RVC_C2_RS1_MASK)); })
> + (RV_X_mask(x_, RVC_C2_RS1_OPOFF, RVC_C2_RS1_MASK)); })
>
> #define RVC_EXTRACT_JTYPE_IMM(x) \
> ({typeof(x) x_ = (x); \
> @@ -346,10 +347,10 @@ static __always_inline bool riscv_insn_is_c_jalr(u32 code)
> (RVC_IMM_SIGN(x_) << RVC_B_IMM_SIGN_OFF); })
>
> #define RVG_EXTRACT_SYSTEM_CSR(x) \
> - ({typeof(x) x_ = (x); RV_X(x_, RVG_SYSTEM_CSR_OFF, RVG_SYSTEM_CSR_MASK); })
> + ({typeof(x) x_ = (x); RV_X_mask(x_, RVG_SYSTEM_CSR_OFF, RVG_SYSTEM_CSR_MASK); })
>
> #define RVFDQ_EXTRACT_FL_FS_WIDTH(x) \
> - ({typeof(x) x_ = (x); RV_X(x_, RVFDQ_FL_FS_WIDTH_OFF, \
> + ({typeof(x) x_ = (x); RV_X_mask(x_, RVFDQ_FL_FS_WIDTH_OFF, \
> RVFDQ_FL_FS_WIDTH_MASK); })
>
> #define RVV_EXTRACT_VL_VS_WIDTH(x) RVFDQ_EXTRACT_FL_FS_WIDTH(x)
> @@ -375,10 +376,10 @@ static inline void riscv_insn_insert_jtype_imm(u32 *insn, s32 imm)
> {
> /* drop the old IMMs, all jal IMM bits sit at 31:12 */
> *insn &= ~GENMASK(31, 12);
> - *insn |= (RV_X(imm, RV_J_IMM_10_1_OFF, RV_J_IMM_10_1_MASK) << RV_J_IMM_10_1_OPOFF) |
> - (RV_X(imm, RV_J_IMM_11_OFF, RV_J_IMM_11_MASK) << RV_J_IMM_11_OPOFF) |
> - (RV_X(imm, RV_J_IMM_19_12_OFF, RV_J_IMM_19_12_MASK) << RV_J_IMM_19_12_OPOFF) |
> - (RV_X(imm, RV_J_IMM_SIGN_OFF, 1) << RV_J_IMM_SIGN_OPOFF);
> + *insn |= (RV_X_mask(imm, RV_J_IMM_10_1_OFF, RV_J_IMM_10_1_MASK) << RV_J_IMM_10_1_OPOFF) |
> + (RV_X_mask(imm, RV_J_IMM_11_OFF, RV_J_IMM_11_MASK) << RV_J_IMM_11_OPOFF) |
> + (RV_X_mask(imm, RV_J_IMM_19_12_OFF, RV_J_IMM_19_12_MASK) << RV_J_IMM_19_12_OPOFF) |
> + (RV_X_mask(imm, RV_J_IMM_SIGN_OFF, 1) << RV_J_IMM_SIGN_OPOFF);
> }
>
> /*
> diff --git a/arch/riscv/kernel/elf_kexec.c b/arch/riscv/kernel/elf_kexec.c
> index e783a72d051f..15e6a8f3d50b 100644
> --- a/arch/riscv/kernel/elf_kexec.c
> +++ b/arch/riscv/kernel/elf_kexec.c
> @@ -336,7 +336,6 @@ static void *elf_kexec_load(struct kimage *image, char *kernel_buf,
> return ret ? ERR_PTR(ret) : NULL;
> }
>
> -#define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1))
> #define RISCV_IMM_BITS 12
> #define RISCV_IMM_REACH (1LL << RISCV_IMM_BITS)
> #define RISCV_CONST_HIGH_PART(x) \
> diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
> index 4354c87c0376..fb2599d62752 100644
> --- a/arch/riscv/kernel/traps_misaligned.c
> +++ b/arch/riscv/kernel/traps_misaligned.c
> @@ -105,7 +105,6 @@
> #define SH_RS2 20
> #define SH_RS2C 2
>
> -#define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1))
> #define RVC_LW_IMM(x) ((RV_X(x, 6, 1) << 2) | \
> (RV_X(x, 10, 3) << 3) | \
> (RV_X(x, 5, 1) << 6))
> diff --git a/arch/riscv/kvm/vcpu_insn.c b/arch/riscv/kvm/vcpu_insn.c
> index 97dec18e6989..ba4813673f95 100644
> --- a/arch/riscv/kvm/vcpu_insn.c
> +++ b/arch/riscv/kvm/vcpu_insn.c
> @@ -91,7 +91,6 @@
> #define SH_RS2C 2
> #define MASK_RX 0x1f
>
> -#define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1))
> #define RVC_LW_IMM(x) ((RV_X(x, 6, 1) << 2) | \
> (RV_X(x, 10, 3) << 3) | \
> (RV_X(x, 5, 1) << 6))
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