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Message-ID: <ed284074-d12a-497d-b8c3-de913bcffb6a@quicinc.com>
Date: Tue, 22 Apr 2025 16:51:12 +0530
From: Viken Dadhaniya <quic_vdadhani@...cinc.com>
To: Bjorn Andersson <andersson@...nel.org>
CC: <konradybcio@...nel.org>, <robh@...nel.org>, <krzk+dt@...nel.org>,
<conor+dt@...nel.org>, <linux-arm-msm@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<quic_msavaliy@...cinc.com>, <quic_anupkulk@...cinc.com>
Subject: Re: [PATCH v2 RESEND] arm64: dts: qcom: sa8775p: Add default pin
configurations for QUP SEs
On 4/20/2025 10:40 PM, Bjorn Andersson wrote:
> On Wed, Apr 16, 2025 at 03:44:11PM +0530, Viken Dadhaniya wrote:
>> Default pinctrl configurations for all QUP (Qualcomm Universal Peripheral)
>> Serial Engines (SEs) are missing in the SoC device tree. These
>> configurations are required by client teams when enabling any SEs as I2C,
>> SPI, or Serial protocols.
>>
>> Add default pin configurations for Serial Engines (SEs) for all supported
>> protocols, including I2C, SPI, and UART, to the sa8775p device tree. This
>> change facilitates slave device driver clients to enable usecase with
>> minimal modifications.
>>
>> Remove duplicate pin configurations from target-specific file as same pin
>> configuration is included in the SoC device tree.
>>
>> Signed-off-by: Viken Dadhaniya <quic_vdadhani@...cinc.com>
>> ---
>> v1 -> v2:
>>
>> - Drop drive-strength and bias property from soc dtsi.
>> - Update commit log.
>>
>> v1 Link: https://lore.kernel.org/lkml/20250225154136.3052757-1-quic_vdadhani@quicinc.com/
>> ---
>> ---
>> arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi | 7 -
>> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 750 +++++++++++++++++++++
>> 2 files changed, 750 insertions(+), 7 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi
>> index 967913169539..17c3f662d14b 100644
>> --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi
>> @@ -712,11 +712,6 @@ ethernet0_mdio: ethernet0-mdio-pins {
>> };
>> };
>>
>> - qup_uart10_default: qup-uart10-state {
>> - pins = "gpio46", "gpio47";
>> - function = "qup1_se3";
>> - };
>> -
>> qup_spi16_default: qup-spi16-state {
>> pins = "gpio86", "gpio87", "gpio88", "gpio89";
>> function = "qup2_se2";
>> @@ -917,8 +912,6 @@ &remoteproc_gpdsp1 {
>>
>> &uart10 {
>> compatible = "qcom,geni-debug-uart";
>> - pinctrl-0 = <&qup_uart10_default>;
>> - pinctrl-names = "default";
>> status = "okay";
>> };
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> [..]
>> + qup_spi16_default: qup-spi16-state {
>> + pins = "gpio86", "gpio87", "gpio88", "gpio89";
>> + function = "qup2_se2";
>> + };
>
> Now we have qup_spi16_default in both sa8775p-ride.dtsi and sa8775p.dtsi
>
> I presume you forgot to clean that up?
Sure will update in next patch.
>
>
> PS. I don't know why the word "RESEND" is present in $subject. Why was
> this resent?
>
Hi Bjorn,
I apologize, but I'm not entirely sure if there has been any approval or
if the patch will be accepted. Since it's been over three weeks, I
thought it might be a good idea to resend it.
I apologize for any confusion caused by resending the patch.
> Regards,
> Bjorn
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