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Message-ID: <aAjufPQnBsR6ysAH@ryzen>
Date: Wed, 23 Apr 2025 15:43:24 +0200
From: Niklas Cassel <cassel@...nel.org>
To: Hans Zhang <18255117159@....com>
Cc: lpieralisi@...nel.org, kw@...ux.com, bhelgaas@...gle.com,
heiko@...ech.de, manivannan.sadhasivam@...aro.org, robh@...nel.org,
jingoohan1@...il.com, shawn.lin@...k-chips.com,
linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-rockchip@...ts.infradead.org
Subject: Re: [PATCH v2 2/3] PCI: dw-rockchip: Reorganize register and
bitfield definitions
On Wed, Apr 23, 2025 at 06:54:14PM +0800, Hans Zhang wrote:
> Register definitions were scattered with ambiguous names (e.g.,
> PCIE_RDLH_LINK_UP_CHGED in PCIE_CLIENT_INTR_STATUS_MISC) and lacked
> hierarchical grouping. Magic values for bit operations reduced code
> clarity.
>
> Group registers and their associated bitfields logically. This improves
> maintainability and aligns the code with hardware documentation.
>
> Signed-off-by: Hans Zhang <18255117159@....com>
> ---
> drivers/pci/controller/dwc/pcie-dw-rockchip.c | 71 ++++++++++++-------
> 1 file changed, 45 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> index fd5827bbfae3..6cf75160fb1c 100644
> --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> @@ -34,30 +34,49 @@
>
> #define to_rockchip_pcie(x) dev_get_drvdata((x)->dev)
>
> -#define PCIE_CLIENT_RC_MODE HIWORD_UPDATE_BIT(0x40)
> -#define PCIE_CLIENT_EP_MODE HIWORD_UPDATE(0xf0, 0x0)
> -#define PCIE_CLIENT_ENABLE_LTSSM HIWORD_UPDATE_BIT(0xc)
> -#define PCIE_CLIENT_DISABLE_LTSSM HIWORD_UPDATE(0x0c, 0x8)
> -#define PCIE_CLIENT_INTR_STATUS_MSG_RX 0x04
> -#define PCIE_CLIENT_INTR_STATUS_MISC 0x10
> -#define PCIE_CLIENT_INTR_MASK_MISC 0x24
> -#define PCIE_CLIENT_POWER 0x2c
> -#define PCIE_CLIENT_MSG_GEN 0x34
> -#define PME_READY_ENTER_L23 BIT(3)
> -#define PME_TURN_OFF (BIT(4) | BIT(20))
> -#define PME_TO_ACK (BIT(9) | BIT(25))
> -#define PCIE_SMLH_LINKUP BIT(16)
> -#define PCIE_RDLH_LINKUP BIT(17)
> -#define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP)
> -#define PCIE_RDLH_LINK_UP_CHGED BIT(1)
> -#define PCIE_LINK_REQ_RST_NOT_INT BIT(2)
> -#define PCIE_CLIENT_GENERAL_CONTROL 0x0
> +/* General Control Register */
> +#define PCIE_CLIENT_GENERAL_CON 0x0
> +#define PCIE_CLIENT_RC_MODE HIWORD_UPDATE_BIT(0x40)
> +#define PCIE_CLIENT_EP_MODE HIWORD_UPDATE(0xf0, 0x0)
> +#define PCIE_CLIENT_ENABLE_LTSSM HIWORD_UPDATE_BIT(0xc)
> +#define PCIE_CLIENT_DISABLE_LTSSM HIWORD_UPDATE(0x0c, 0x8)
> +
> +/* Interrupt Status Register Related to Message Reception */
> +#define PCIE_CLIENT_INTR_STATUS_MSG_RX 0x4
> +
> +/* Interrupt Status Register Related to Legacy Interrupt */
> #define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8
> +
> +/* Interrupt Status Register Related to Miscellaneous Operation */
double spaces, other comments just have one space.
> +#define PCIE_CLIENT_INTR_STATUS_MISC 0x10
> +#define PCIE_RDLH_LINK_UP_CHGED BIT(1)
> +#define PCIE_LINK_REQ_RST_NOT_INT BIT(2)
> +
> +/* Interrupt Mask Register Related to Legacy Interrupt */
> #define PCIE_CLIENT_INTR_MASK_LEGACY 0x1c
> +
> +/* Interrupt Mask Register Related to Miscellaneous Operation */
> +#define PCIE_CLIENT_INTR_MASK_MISC 0x24
> +
> +/* Power Management Control Register */
> +#define PCIE_CLIENT_POWER_CON 0x2c
> +#define PME_READY_ENTER_L23 BIT(3)
> +
> +/* Message Generation Control Register */
double spaces, other comments just have one space.
> +#define PCIE_CLIENT_MSG_GEN_CON 0x34
> +#define PME_TURN_OFF HIWORD_UPDATE_BIT(BIT(4))
> +#define PME_TO_ACK HIWORD_UPDATE_BIT(BIT(9))
> +
> +/* Hot Reset Control Register */
> #define PCIE_CLIENT_HOT_RESET_CTRL 0x180
> +#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4)
> +
> +/* LTSSM Status Register */
> #define PCIE_CLIENT_LTSSM_STATUS 0x300
> -#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4)
> -#define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0)
> +#define PCIE_SMLH_LINKUP BIT(16)
> +#define PCIE_RDLH_LINKUP BIT(17)
> +#define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP)
> +#define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0)
>
> struct rockchip_pcie {
> struct dw_pcie pci;
> @@ -176,13 +195,13 @@ static u32 rockchip_pcie_get_pure_ltssm(struct dw_pcie *pci)
> static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip)
> {
> rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_ENABLE_LTSSM,
> - PCIE_CLIENT_GENERAL_CONTROL);
> + PCIE_CLIENT_GENERAL_CON);
> }
>
> static void rockchip_pcie_disable_ltssm(struct rockchip_pcie *rockchip)
> {
> rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_DISABLE_LTSSM,
> - PCIE_CLIENT_GENERAL_CONTROL);
> + PCIE_CLIENT_GENERAL_CON);
> }
>
> static int rockchip_pcie_link_up(struct dw_pcie *pci)
> @@ -274,8 +293,8 @@ static void rockchip_pcie_pme_turn_off(struct dw_pcie_rp *pp)
> u32 status;
>
> /* 1. Broadcast PME_Turn_Off Message, bit 4 self-clear once done */
> - rockchip_pcie_writel_apb(rockchip, PME_TURN_OFF, PCIE_CLIENT_MSG_GEN);
> - ret = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_MSG_GEN,
> + rockchip_pcie_writel_apb(rockchip, PME_TURN_OFF, PCIE_CLIENT_MSG_GEN_CON);
> + ret = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_MSG_GEN_CON,
> status, !(status & BIT(4)), PCIE_PME_TO_L2_TIMEOUT_US / 10,
> PCIE_PME_TO_L2_TIMEOUT_US);
> if (ret) {
> @@ -294,7 +313,7 @@ static void rockchip_pcie_pme_turn_off(struct dw_pcie_rp *pp)
>
> /* 3. Clear PME_TO_Ack and Wait for ready to enter L23 message */
> rockchip_pcie_writel_apb(rockchip, PME_TO_ACK, PCIE_CLIENT_INTR_STATUS_MSG_RX);
> - ret = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_POWER,
> + ret = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_POWER_CON,
> status, status & PME_READY_ENTER_L23,
> PCIE_PME_TO_L2_TIMEOUT_US / 10,
> PCIE_PME_TO_L2_TIMEOUT_US);
> @@ -552,7 +571,7 @@ static void rockchip_pcie_ltssm_enable_control_mode(struct rockchip_pcie *rockch
> val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE);
> rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL);
>
> - rockchip_pcie_writel_apb(rockchip, mode, PCIE_CLIENT_GENERAL_CONTROL);
> + rockchip_pcie_writel_apb(rockchip, mode, PCIE_CLIENT_GENERAL_CON);
I can see why you renamed PCIE_CLIENT_GENERAL_CONTROL to PCIE_CLIENT_GENERAL_CON
(to match PCIE_CLIENT_MSG_GEN_CON).
But now we have PCIE_CLIENT_MSG_GEN_CON / PCIE_CLIENT_GENERAL_CON and
PCIE_CLIENT_HOT_RESET_CTRL.
_CTRL seems like a more common shortening. How about renaming all three to
end with _CTRL ?
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