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Message-ID: <agbftnk7uqj6e2zyw3igxlp3cctl6xhk6ix4gp6u5dot7nf3fm@cipkx222ffo5>
Date: Wed, 23 Apr 2025 17:02:10 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
To: Shazad Hussain <quic_shazhuss@...cinc.com>
Cc: Deepti Jaggi <quic_djaggi@...cinc.com>, andersson@...nel.org,
konradybcio@...nel.org, robh@...nel.org, krzk+dt@...nel.org,
conor+dt@...nel.org, quic_psodagud@...cinc.com,
quic_ptalari@...cinc.com, linux-arm-msm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3] arm64: dts: qcom: add initial support for qcom
sa8255p-ride
On Wed, Apr 23, 2025 at 10:16:57AM +0530, Shazad Hussain wrote:
>
>
> On 4/23/2025 4:42 AM, Deepti Jaggi wrote:
> > From: Nikunj Kela <quic_nkela@...cinc.com>
> >
> > This adds basic support for the Qualcomm sa8255p platform and the
> > reference board: sa8255p-ride. The dt files describe the basics of the
> > SoC and enable booting to shell with ramdisk.
> >
> > The Qualcomm automotive sa8255p SoC utilizes firmware to configure platform
> > resources such as clocks, interconnects, and TLMM. Device drivers request
> > these resources through the SCMI power and performance protocols. The SCMI
> > platform supports resource aggregation and handles parallel requests from
> > agents, with each driver having a dedicated SCMI channel for communication.
> >
> > Co-developed-by: Shazad Hussain <quic_shazhuss@...cinc.com>
> > Signed-off-by: Shazad Hussain <quic_shazhuss@...cinc.com>
> > Signed-off-by: Nikunj Kela <quic_nkela@...cinc.com>
> > Signed-off-by: Deepti Jaggi <quic_djaggi@...cinc.com>
> > ---
> > This patch is dependent on [2] for booting to shell and DT bindings.
> >
> > Changes in v3:
> > Removed the patches from original series [1].
> > Added arm,max-msg and arm,max-msg-size DT property in scmi nodes.
> > Changed max-rx-timeout-ms to arm,max-rx-timeout-ms in scmi nodes.
> > Updated commit text.
> > Reordered range property for qupv3_id_0, qupv3_id_1 and qupv3_id_3 nodes.
> > Reordered vendor property(#qcom,sensors) for tsens* nodes.
> > Changed cache labels to lower case.
> > Removed unused i2c,spi and tlmm nodes.
> > Updated reserved memory nodes.
> >
> > Changes in v2:
> > Removed scmichannels label and alias
> > Modified scmi node name to conform to schema
> > Moved status property to be the last one in scmi instances
> > Changed to lower case for cpu labels
> > Added fallback compatible for tlmm node
> >
> > [1]: https://lore.kernel.org/all/20240903220240.2594102-1-quic_nkela@quicinc.com/
> > [2]: https://lore.kernel.org/all/20250418151235.27787-1-quic_ptalari@quicinc.com/
> > ---
> > arch/arm64/boot/dts/qcom/Makefile | 1 +
> > arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi | 80 +
> > arch/arm64/boot/dts/qcom/sa8255p-ride.dts | 94 +
> > arch/arm64/boot/dts/qcom/sa8255p-scmi.dtsi | 2440 +++++++++++++++++++
> > arch/arm64/boot/dts/qcom/sa8255p.dtsi | 2075 ++++++++++++++++
> > 5 files changed, 4690 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi
> > create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-ride.dts
> > create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-scmi.dtsi
> > create mode 100644 arch/arm64/boot/dts/qcom/sa8255p.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> > index adb4d026bcc4..7437e51e5849 100644
> > --- a/arch/arm64/boot/dts/qcom/Makefile
> > +++ b/arch/arm64/boot/dts/qcom/Makefile
> > @@ -134,6 +134,7 @@ qrb5165-rb5-vision-mezzanine-dtbs := qrb5165-rb5.dtb qrb5165-rb5-vision-mezzanin
> > dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5-vision-mezzanine.dtb
> > dtb-$(CONFIG_ARCH_QCOM) += qru1000-idp.dtb
> > dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb
> > +dtb-$(CONFIG_ARCH_QCOM) += sa8255p-ride.dtb
> > dtb-$(CONFIG_ARCH_QCOM) += sa8295p-adp.dtb
> > dtb-$(CONFIG_ARCH_QCOM) += sa8540p-ride.dtb
> > dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride.dtb
> > diff --git a/arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi b/arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi
> > new file mode 100644
> > index 000000000000..b00c2b05cef7
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi
> > @@ -0,0 +1,80 @@
> > +// SPDX-License-Identifier: BSD-3-Clause
> > +/*
> > + * Copyright (c) 2024-2025, Qualcomm Innovation Center, Inc. All rights reserved.
> > + */
> > +
> > +/ {
> > + thermal-zones {
> > + pmm8654au_0_thermal: pm8255-0-thermal {
> > + polling-delay-passive = <100>;
> > +
> > + trips {
> > + trip0 {
> > + temperature = <105000>;
> > + hysteresis = <0>;
> > + type = "passive";
> > + };
> > +
> > + trip1 {
> > + temperature = <125000>;
> > + hysteresis = <0>;
> > + type = "critical";
> > + };
> > + };
> > + };
> > +
> > + pmm8654au_1_thermal: pm8255-1-thermal {
> > + polling-delay-passive = <100>;
> > +
> > + trips {
> > + trip0 {
> > + temperature = <105000>;
> > + hysteresis = <0>;
> > + type = "passive";
> > + };
> > +
> > + trip1 {
> > + temperature = <125000>;
> > + hysteresis = <0>;
> > + type = "critical";
> > + };
> > + };
> > + };
> > +
> > + pmm8654au_2_thermal: pm8255-2-thermal {
> > + polling-delay-passive = <100>;
> > +
> > + trips {
> > + trip0 {
> > + temperature = <105000>;
> > + hysteresis = <0>;
> > + type = "passive";
> > + };
> > +
> > + trip1 {
> > + temperature = <125000>;
> > + hysteresis = <0>;
> > + type = "critical";
> > + };
> > + };
> > + };
> > +
> > + pmm8654au_3_thermal: pm8255-3-thermal {
> > + polling-delay-passive = <100>;
> > +
> > + trips {
> > + trip0 {
> > + temperature = <105000>;
> > + hysteresis = <0>;
> > + type = "passive";
> > + };
> > +
> > + trip1 {
> > + temperature = <125000>;
> > + hysteresis = <0>;
> > + type = "critical";
> > + };
> > + };
> > + };
> > + };
> > +};
>
> PMIC is handled by firmware on this SoC and in my openion we do not need
> to have a dedicated sa8255p-pmics.dtsi only to have thermal zones nodes.
> Can we keep these pmic thermal zones to sa8255p.dtsi with other thermal
> zones nodes ?
For the PMIC? No, they are not a part of the SoC.
--
With best wishes
Dmitry
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