| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <2m5fq7whbvaq4sbbxittxhbksw6erfotlwalrfevujq4mrt3kk@ctbgwinz2o72>
Date: Wed, 23 Apr 2025 17:23:32 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
To: Abhinav Kumar <quic_abhinavk@...cinc.com>
Cc: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
Rob Clark <robdclark@...il.com>, Sean Paul <sean@...rly.run>,
Marijn Suijten <marijn.suijten@...ainline.org>,
David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Maxime Ripard <mripard@...nel.org>,
Thomas Zimmermann <tzimmermann@...e.de>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Kuogee Hsieh <quic_khsieh@...cinc.com>,
Mahadevan <quic_mahap@...cinc.com>, linux-arm-msm@...r.kernel.org,
dri-devel@...ts.freedesktop.org, freedreno@...ts.freedesktop.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 3/4] dt-bindings: display/msm: add stream 1 pixel clock
binding
On Tue, Apr 22, 2025 at 07:46:57PM -0700, Abhinav Kumar wrote:
>
>
> On 12/3/2024 5:43 AM, Dmitry Baryshkov wrote:
> > On Mon, Dec 02, 2024 at 07:31:41PM -0800, Abhinav Kumar wrote:
> > > On some chipsets the display port controller can support more
> > > than one pixel stream (multi-stream transport). To support MST
> > > on such chipsets, add the binding for stream 1 pixel clock for
> > > display port controller. Since this mode is not supported on all
> > > chipsets, add exception rules and min/max items to clearly mark
> > > which chipsets support only SST mode (single stream) and which ones
> > > support MST.
> > >
> > > Signed-off-by: Abhinav Kumar <quic_abhinavk@...cinc.com>
> > > ---
> > > .../bindings/display/msm/dp-controller.yaml | 32 ++++++++++++++++++++++
> > > .../bindings/display/msm/qcom,sa8775p-mdss.yaml | 9 ++++--
> > > 2 files changed, 38 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
> > > index 9fe2bf0484d8..650d19e58277 100644
> > > --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
> > > +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
> > > @@ -50,30 +50,38 @@ properties:
> > > maxItems: 1
> > > clocks:
> > > + minItems: 5
> > > items:
> > > - description: AHB clock to enable register access
> > > - description: Display Port AUX clock
> > > - description: Display Port Link clock
> > > - description: Link interface clock between DP and PHY
> > > - description: Display Port stream 0 Pixel clock
> > > + - description: Display Port stream 1 Pixel clock
> > > clock-names:
> > > + minItems: 5
> > > items:
> > > - const: core_iface
> > > - const: core_aux
> > > - const: ctrl_link
> > > - const: ctrl_link_iface
> > > - const: stream_pixel
> > > + - const: stream_1_pixel
> > > assigned-clocks:
> > > + minItems: 2
> > > items:
> > > - description: link clock source
> > > - description: stream 0 pixel clock source
> > > + - description: stream 1 pixel clock source
> > > assigned-clock-parents:
> > > + minItems: 2
> > > items:
> > > - description: Link clock PLL output provided by PHY block
> > > - description: Stream 0 pixel clock PLL output provided by PHY block
> > > + - description: Stream 1 pixel clock PLL output provided by PHY block
> > > phys:
> > > maxItems: 1
> > > @@ -175,6 +183,30 @@ allOf:
> > > required:
> > > - "#sound-dai-cells"
> > > + - if:
> > > + properties:
> > > + compatible:
> > > + contains:
> > > + enum:
> > > + - qcom,sa8775p-dp
> >
> > Why do you need an extra platform conditional?
> >
>
> I expect this list to grow and also there can be chipsets which support 4
> streams as well, so an extra platform conditional was needed.
Ack
>
> > > +
> > > + then:
> > > + properties:
> > > + clocks:
> > > + maxItems: 6
> > > + clock-names:
> > > + items:
> > > + - const: core_iface
> > > + - const: core_aux
> > > + - const: ctrl_link
> > > + - const: ctrl_link_iface
> > > + - const: stream_pixel
> > > + - const: stream_1_pixel
You don't need to ducplicate the list. Just specify min/maxItems.
> > > + assigned-clocks:
> > > + maxItems: 3
> > > + assigned-clock-parents:
> > > + maxItems: 3
> > > +
> > > additionalProperties: false
> > > examples:
> > > diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
> > > index 58f8a01f29c7..7f10e6ad8f63 100644
> > > --- a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
> > > +++ b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
> > > @@ -177,16 +177,19 @@ examples:
> > > <&dispcc_dptx0_aux_clk>,
> > > <&dispcc_dptx0_link_clk>,
> > > <&dispcc_dptx0_link_intf_clk>,
> > > - <&dispcc_dptx0_pixel0_clk>;
> > > + <&dispcc_dptx0_pixel0_clk>,
> > > + <&dispcc_dptx0_pixel1_clk>;
> > > clock-names = "core_iface",
> > > "core_aux",
> > > "ctrl_link",
> > > "ctrl_link_iface",
> > > - "stream_pixel";
> > > + "stream_pixel",
> > > + "stream_1_pixel";
> > > assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>,
> > > + <&dispcc_mdss_dptx0_pixel1_clk_src>,
> > > <&dispcc_mdss_dptx0_pixel0_clk_src>;
> > > - assigned-clock-parents = <&mdss0_edp_phy 0>, <&mdss0_edp_phy 1>;
> > > + assigned-clock-parents = <&mdss0_edp_phy 0>, <&mdss0_edp_phy 1>, <&mdss0_edp_phy 1>;
> > > phys = <&mdss0_edp_phy>;
> > > phy-names = "dp";
> > >
> > > --
> > > 2.34.1
> > >
> >
>
--
With best wishes
Dmitry
Powered by blists - more mailing lists