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Message-Id: <20250423-spmi-nvmem-v3-3-2985aa722ddc@gmail.com>
Date: Wed, 23 Apr 2025 19:55:15 +0200
From: Sasha Finkelstein via B4 Relay <devnull+fnkl.kernel.gmail.com@...nel.org>
To: Sven Peter <sven@...npeter.dev>, Janne Grunau <j@...nau.net>,
Alyssa Rosenzweig <alyssa@...enzweig.io>, Neal Gompa <neal@...pa.dev>,
Srinivas Kandagatla <srinivas.kandagatla@...aro.org>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>
Cc: asahi@...ts.linux.dev, linux-arm-kernel@...ts.infradead.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Sasha Finkelstein <fnkl.kernel@...il.com>, Hector Martin <marcan@...can.st>,
Nick Chan <towinchenmi@...il.com>
Subject: [PATCH v3 3/3] arm64: dts: apple: Add PMIC NVMEM
From: Hector Martin <marcan@...can.st>
Add device tree entries for NVMEM cells present on the PMIC
Signed-off-by: Hector Martin <marcan@...can.st>
Reviewed-by: Nick Chan <towinchenmi@...il.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@...enzweig.io>
Co-developed-by: Sasha Finkelstein <fnkl.kernel@...il.com>
Signed-off-by: Sasha Finkelstein <fnkl.kernel@...il.com>
---
arch/arm64/boot/dts/apple/t6001.dtsi | 1 +
arch/arm64/boot/dts/apple/t6002.dtsi | 1 +
arch/arm64/boot/dts/apple/t600x-die0.dtsi | 50 +++++++++++++++++++++++++++++++
arch/arm64/boot/dts/apple/t8103.dtsi | 50 +++++++++++++++++++++++++++++++
arch/arm64/boot/dts/apple/t8112.dtsi | 50 +++++++++++++++++++++++++++++++
5 files changed, 152 insertions(+)
diff --git a/arch/arm64/boot/dts/apple/t6001.dtsi b/arch/arm64/boot/dts/apple/t6001.dtsi
index 620b17e4031f069874aaabadbf06b7b29ec4031e..d2cf81926f284ccf7627701cc82edff31d4d72d6 100644
--- a/arch/arm64/boot/dts/apple/t6001.dtsi
+++ b/arch/arm64/boot/dts/apple/t6001.dtsi
@@ -11,6 +11,7 @@
#include <dt-bindings/interrupt-controller/apple-aic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/apple.h>
+#include <dt-bindings/spmi/spmi.h>
#include "multi-die-cpp.h"
diff --git a/arch/arm64/boot/dts/apple/t6002.dtsi b/arch/arm64/boot/dts/apple/t6002.dtsi
index a963a5011799a0480f88688fb4372a31f0bbf806..e36f422d257d8fe3a62bfa6e0f0e0dc6c34608a4 100644
--- a/arch/arm64/boot/dts/apple/t6002.dtsi
+++ b/arch/arm64/boot/dts/apple/t6002.dtsi
@@ -11,6 +11,7 @@
#include <dt-bindings/interrupt-controller/apple-aic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/apple.h>
+#include <dt-bindings/spmi/spmi.h>
#include "multi-die-cpp.h"
diff --git a/arch/arm64/boot/dts/apple/t600x-die0.dtsi b/arch/arm64/boot/dts/apple/t600x-die0.dtsi
index 4c224e686ffe5602329f7f394d3354559c4130ab..110bc6719512e334e04b496fb157cb4368679957 100644
--- a/arch/arm64/boot/dts/apple/t600x-die0.dtsi
+++ b/arch/arm64/boot/dts/apple/t600x-die0.dtsi
@@ -50,6 +50,56 @@ nub_spmi0: spmi@...0a1300 {
reg = <0x2 0x920a1300 0x0 0x100>;
#address-cells = <2>;
#size-cells = <0>;
+
+ pmic1: pmic@f {
+ compatible = "apple,maverick-pmic", "apple,spmi-nvmem";
+ reg = <0xf SPMI_USID>;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ pm_setting: pm-setting@...5 {
+ reg = <0x1405 0x1>;
+ };
+
+ rtc_offset: rtc-offset@...1 {
+ reg = <0x1411 0x6>;
+ };
+
+ boot_stage: boot-stage@...1 {
+ reg = <0x6001 0x1>;
+ };
+
+ boot_error_count: boot-error-count@...2 {
+ reg = <0x6002 0x1>;
+ bits = <0 4>;
+ };
+
+ panic_count: panic-count@...2 {
+ reg = <0x6002 0x1>;
+ bits = <4 4>;
+ };
+
+ boot_error_stage: boot-error-stage@...3 {
+ reg = <0x6003 0x1>;
+ };
+
+ shutdown_flag: shutdown-flag@...f {
+ reg = <0x600f 0x1>;
+ bits = <3 1>;
+ };
+
+ fault_shadow: fault-shadow@...b {
+ reg = <0x867b 0x10>;
+ };
+
+ socd: socd@...0 {
+ reg = <0x8b00 0x400>;
+ };
+ };
+ };
};
wdt: watchdog@...2b0000 {
diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/apple/t8103.dtsi
index bdb1cb9e406a441e458b1c735359b0148146e91b..20faf0c0d80927b2e18dd966a61b5507b322c72f 100644
--- a/arch/arm64/boot/dts/apple/t8103.dtsi
+++ b/arch/arm64/boot/dts/apple/t8103.dtsi
@@ -747,6 +747,56 @@ nub_spmi: spmi@...0d9300 {
reg = <0x2 0x3d0d9300 0x0 0x100>;
#address-cells = <2>;
#size-cells = <0>;
+
+ pmic1: pmic@f {
+ compatible = "apple,sera-pmic", "apple,spmi-nvmem";
+ reg = <0xf SPMI_USID>;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ boot_stage: boot-stage@...1 {
+ reg = <0x9f01 0x1>;
+ };
+
+ boot_error_count: boot-error-count@...2 {
+ reg = <0x9f02 0x1>;
+ bits = <0 4>;
+ };
+
+ panic_count: panic-count@...2 {
+ reg = <0x9f02 0x1>;
+ bits = <4 4>;
+ };
+
+ boot_error_stage: boot-error-stage@...3 {
+ reg = <0x9f03 0x1>;
+ };
+
+ shutdown_flag: shutdown-flag@...f {
+ reg = <0x9f0f 0x1>;
+ bits = <3 1>;
+ };
+
+ fault_shadow: fault-shadow@...b {
+ reg = <0xa67b 0x10>;
+ };
+
+ socd: socd@...0 {
+ reg = <0xab00 0x400>;
+ };
+
+ pm_setting: pm-setting@...1 {
+ reg = <0xd001 0x1>;
+ };
+
+ rtc_offset: rtc-offset@...0 {
+ reg = <0xd100 0x6>;
+ };
+ };
+ };
};
pinctrl_nub: pinctrl@...1f0000 {
diff --git a/arch/arm64/boot/dts/apple/t8112.dtsi b/arch/arm64/boot/dts/apple/t8112.dtsi
index 950d1f906ba3023c1d118179207a2099345aae94..e95711d8337f6cea898e88a3d564caf2c4f94404 100644
--- a/arch/arm64/boot/dts/apple/t8112.dtsi
+++ b/arch/arm64/boot/dts/apple/t8112.dtsi
@@ -787,6 +787,56 @@ nub_spmi: spmi@...714000 {
reg = <0x2 0x3d714000 0x0 0x100>;
#address-cells = <2>;
#size-cells = <0>;
+
+ pmic1: pmic@e {
+ compatible = "apple,stowe-pmic", "apple,spmi-nvmem";
+ reg = <0xe SPMI_USID>;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ fault_shadow: fault-shadow@...b {
+ reg = <0x867b 0x10>;
+ };
+
+ socd: socd@...0 {
+ reg = <0x8b00 0x400>;
+ };
+
+ boot_stage: boot-stage@...1 {
+ reg = <0xf701 0x1>;
+ };
+
+ boot_error_count: boot-error-count@...2 {
+ reg = <0xf702 0x1>;
+ bits = <0 4>;
+ };
+
+ panic_count: panic-count@...2 {
+ reg = <0xf702 0x1>;
+ bits = <4 4>;
+ };
+
+ boot_error_stage: boot-error-stage@...3 {
+ reg = <0xf703 0x1>;
+ };
+
+ shutdown_flag: shutdown-flag@...f {
+ reg = <0xf70f 0x1>;
+ bits = <3 1>;
+ };
+
+ pm_setting: pm-setting@...1 {
+ reg = <0xf801 0x1>;
+ };
+
+ rtc_offset: rtc-offset@...0 {
+ reg = <0xf900 0x6>;
+ };
+ };
+ };
};
pinctrl_smc: pinctrl@...820000 {
--
2.49.0
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