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Message-ID: <e9ec2ef2-01ca-4648-b788-d427f05126f1@altera.com>
Date: Wed, 23 Apr 2025 14:43:34 -0700
From: "Gerlach, Matthew" <matthew.gerlach@...era.com>
To: Rob Herring <robh@...nel.org>
Cc: krzk+dt@...nel.org, conor+dt@...nel.org, mturquette@...libre.com,
sboyd@...nel.org, dinguyen@...nel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org
Subject: Re: [PATCH v2] dt-bindings: clock: socfpga: convert to yaml
On 4/23/2025 1:07 PM, Rob Herring wrote:
>
> On Wed, Apr 23, 2025 at 08:03:18AM -0700, Matthew Gerlach wrote:
>> Convert the clock device tree bindings to yaml for the Altera SoCFPGA
>> Cyclone5, Arria5, and Arria10 chip families. Since the clock nodes are
>> subnodes to Altera SOCFPGA Clock Manager, the yaml was added to
>> socfpga-clk-manager.yaml.
>>
>> Signed-off-by: Matthew Gerlach <matthew.gerlach@...era.com>
>> ---
>> v2:
>> - Fix node name regexs.
>> - Remove redundant type for clocks.
>> - Put repeated properties under '$defs'.
>> - Move reg property after compatible.
>> ---
>> .../arm/altera/socfpga-clk-manager.yaml | 129 +++++++++++++++++-
>> .../bindings/clock/altr_socfpga.txt | 30 ----
>> 2 files changed, 128 insertions(+), 31 deletions(-)
>> delete mode 100644 Documentation/devicetree/bindings/clock/altr_socfpga.txt
>>
>> diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.yaml b/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.yaml
>> index 572381306681..6f09458f22a4 100644
>> --- a/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.yaml
>> +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.yaml
>> @@ -9,20 +9,147 @@ title: Altera SOCFPGA Clock Manager
>> maintainers:
>> - Dinh Nguyen <dinguyen@...nel.org>
>>
>> -description: test
>> +description:
>> + This binding describes the Altera SOCFGPA Clock Manager and its associated
>> + tree of clocks, pll's, and clock gates for the Cyclone5, Arria5 and Arria10
>> + chip families.
>>
>> properties:
>> compatible:
>> items:
>> - const: altr,clk-mgr
>> +
>> reg:
>> maxItems: 1
>>
>> + clocks:
>> + type: object
>> + additionalProperties: false
>> +
>> + properties:
>> + "#address-cells":
>> + const: 1
>> +
>> + "#size-cells":
>> + const: 0
>> +
>> + patternProperties:
>> + "^osc[0-9]$":
>> + type: object
>> +
>> + "^[a-z0-9,_]+(clk|pll|clk_gate|clk_divided)(@[a-f0-9]+)?$":
>> + type: object
>> + additionalProperties: false
>
> Add another level to $defs and move the reference here:
>
> $ref: '#/$defs/clock-props'
> unevaluatedProperties: false
>
> You can also move 'reg' and '#clock-cells' into $defs/clock-props.
>
>> +
>> + properties:
>> +
>> + compatible:
>> + enum:
>> + - altr,socfpga-pll-clock
>> + - altr,socfpga-perip-clk
>> + - altr,socfpga-gate-clk
>> + - altr,socfpga-a10-pll-clock
>> + - altr,socfpga-a10-perip-clk
>> + - altr,socfpga-a10-gate-clk
>> + - fixed-clock
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + clocks:
>> + description: one or more phandles to input clock
>> + minItems: 1
>> + maxItems: 5
>> +
>> + "#address-cells":
>> + const: 1
>> +
>> + "#clock-cells":
>> + const: 0
>> +
>> + "#size-cells":
>> + const: 0
>> +
>
>> + clk-gate:
>> + $ref: '#/$defs/clk-gate'
>> + unevaluatedProperties: false
>> +
>> + div-reg:
>> + $ref: '#/$defs/div-reg'
>> + unevaluatedProperties: false
>> +
>> + fixed-divider:
>> + $ref: '#/$defs/fixed-divider'
>> + unevaluatedProperties: false
>
> And then drop all these. Same in the child node below.
Thank you for the great suggestion,
Matthew Gerlach
>
>> +
>> + patternProperties:
>> + "^[a-z0-9,_]+(clk|pll)(@[a-f0-9]+)?$":
>> + type: object
>> + additionalProperties: false
>> +
>> + properties:
>> + compatible:
>> + enum:
>> + - altr,socfpga-perip-clk
>> + - altr,socfpga-gate-clk
>> + - altr,socfpga-a10-perip-clk
>> + - altr,socfpga-a10-gate-clk
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + "#clock-cells":
>> + const: 0
>> +
>> + clocks:
>> + description: one or more phandles to input clock
>> + minItems: 1
>> + maxItems: 4
>> +
>> + clk-gate:
>> + $ref: '#/$defs/clk-gate'
>> + unevaluatedProperties: false
>> +
>> + div-reg:
>> + $ref: '#/$defs/div-reg'
>> + unevaluatedProperties: false
>> +
>> + fixed-divider:
>> + $ref: '#/$defs/fixed-divider'
>> + unevaluatedProperties: false
>> +
>> + required:
>> + - compatible
>> + - clocks
>> + - "#clock-cells"
>> +
>> + required:
>> + - compatible
>> + - "#clock-cells"
>> +
>> required:
>> - compatible
>> + - reg
>>
>> additionalProperties: false
>>
>> +$defs:
>> + clk-gate:
>> + $ref: /schemas/types.yaml#/definitions/uint32-array
>> + items:
>> + - description: gating register offset
>> + - description: bit index
>> +
>> + div-reg:
>> + $ref: /schemas/types.yaml#/definitions/uint32-array
>> + items:
>> + - description: divider register offset
>> + - description: bit shift
>> + - description: bit width
>> +
>> + fixed-divider:
>> + $ref: /schemas/types.yaml#/definitions/uint32
>> +
>> examples:
>> - |
>> clkmgr@...04000 {
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