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Message-ID: <20250423225405.139613-4-joelagnelf@nvidia.com> Date: Wed, 23 Apr 2025 18:53:59 -0400 From: Joel Fernandes <joelagnelf@...dia.com> To: linux-kernel@...r.kernel.org, Danilo Krummrich <dakr@...nel.org>, Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>, Maxime Ripard <mripard@...nel.org>, Thomas Zimmermann <tzimmermann@...e.de>, David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>, Jonathan Corbet <corbet@....net> Cc: nouveau@...ts.freedesktop.org, dri-devel@...ts.freedesktop.org, Alexandre Courbot <acourbot@...dia.com>, John Hubbard <jhubbard@...dia.com>, Shirish Baskaran <sbaskaran@...dia.com>, Alistair Popple <apopple@...dia.com>, Timur Tabi <ttabi@...dia.com>, Ben Skeggs <bskeggs@...dia.com>, Joel Fernandes <joelagnelf@...dia.com>, linux-doc@...r.kernel.org Subject: [PATCH 3/6] nova-core: docs: Document vbios layout Add detailed explanation and block diagrams of the layout of the vBIOS on Nvidia GPUs. This is important to understand how nova-core boots an Nvidia GPU. Signed-off-by: Joel Fernandes <joelagnelf@...dia.com> --- Documentation/gpu/nova/core/vbios.rst | 154 ++++++++++++++++++++++++++ 1 file changed, 154 insertions(+) create mode 100644 Documentation/gpu/nova/core/vbios.rst diff --git a/Documentation/gpu/nova/core/vbios.rst b/Documentation/gpu/nova/core/vbios.rst new file mode 100644 index 000000000000..17411f21b410 --- /dev/null +++ b/Documentation/gpu/nova/core/vbios.rst @@ -0,0 +1,154 @@ +.. SPDX-License-Identifier: (GPL-2.0+ OR MIT) +========== +VBIOS +========== + +This document describes the layout of the VBIOS image which is a series of concatenated +images in the ROM of the GPU. The VBIOS is mirrored onto the BAR 0 space and is read +by both Boot ROM firmware (also known as IFR or init-from-rom firmware) on the GPU to +boot strap various microcontrollers (PMU, SEC, GSP) with critical initialization before +the driver loads, as well as by the nova-core driver in the kernel to boot the GSP. + +The format of the images in the ROM follow the "BIOS Specification" part of the +PCI specification, with Nvidia-specific extensions. + +As an example, the following are the different image types that can be found in the +VBIOS of an Ampere GA102 GPU which is supported by the nova-core driver. + +- PciAt Image (Type 0x00) - This is the standard PCI BIOS image who's naming likely + comes from the "IBM PC/AT" architecture. + +- EFI Image (Type 0x03) - This is the EFI BIOS image. It contains the UEFI GOP + driver that is used to display UEFI graphics output. + +- First FwSec Image (Type 0xE0) - The first FwSec image (Secure Firmware) + +- Second FwSec Image (Type 0xE0) - The second FwSec image (Secure Firmware) contains + various microcodes that do a range of different functions - all in high secure mode + where they are allowed to perform highly privileged register accesses that the CPU + cannot do. The 2 most important parts (also known as Application Interfaces) of this + are: + 1. The devinit engine - this is loaded ontop the PMU before the driver loads + and interprets devinit commands which perform critical hardware initialization. + This will be described in a separate document. + 2. The DMEM mapper - this is loaded onto the GSP and one of the commands it + performs is carving out the WPR2 area (Write protected region) and placing + important data called 'FRTS' into it which contains things like voltage/frequency + curves etc. + +It is not clear why FwSec has 2 different images, but they both are of type 0xE0 +and can be identified as such. + +VBIOS ROM Layout +---------------- + +The VBIOS layout is roughly a series of concatenated images as follows: +(For more explanations of acronyms, see the detailed descriptions in vbios.rs). + +┌────────────────────────────────────────────────────────────────────────┐ +│ VBIOS (Starting at ROM_OFFSET: 0x300000) │ +├────────────────────────────────────────────────────────────────────────┤ +│ ┌───────────────────────────────────────────────┐ │ +│ │ PciAt Image (Type 0x00) │ │ +│ ├───────────────────────────────────────────────┤ │ +│ │ ┌───────────────────┐ │ │ +│ │ │ ROM Header │ │ │ +│ │ │ (Signature 0xAA55)│ │ │ +│ │ └───────────────────┘ │ │ +│ │ │ rom header's pci_data_struct_offset │ │ +│ │ │ points to the PCIR structure │ │ +│ │ V │ │ +│ │ ┌───────────────────┐ │ │ +│ │ │ PCIR Structure │ │ │ +│ │ │ (Signature "PCIR")│ │ │ +│ │ │ last_image: 0x80 │ │ │ +│ │ │ image_len: size │ │ │ +│ │ │ in 512-byte units │ │ │ +│ │ └───────────────────┘ │ │ +│ │ │ │ │ +│ │ │ NPDE immediately follows PCIR │ │ +│ │ V │ │ +│ │ ┌───────────────────┐ │ │ +│ │ │ NPDE Structure │ │ │ +│ │ │ (Signature "NPDE")│ │ │ +│ │ │ last_image: 0x00 │ │ │ +│ │ └───────────────────┘ │ │ +│ │ │ │ +│ │ ┌───────────────────┐ │ │ +│ │ │ BIT Header │ (Signature scanning │ │ +│ │ │ (Signature "BIT") │ provides the location │ │ +│ │ └───────────────────┘ of the BIT table) │ │ +│ │ │ header is │ │ +│ │ | followed by a table of tokens │ │ +│ │ V one of which is for falcon data. │ │ +│ │ ┌───────────────────┐ │ │ +│ │ │ BIT Tokens │ │ │ +| | | ______________ | | | +│ │ │ │ Falcon Data │ │ │ │ +│ │ │ │ Token (0x70)│---+------------>------------┼──+ │ +│ │ │ └─────────────┘ │ falcon_data_ptr() │ │ │ +│ │ └───────────────────┘ │ V │ +│ └───────────────────────────────────────────────┘ │ │ +│ (no gap between images) │ │ +│ ┌───────────────────────────────────────────────┐ │ │ +│ │ EFI Image (Type 0x03) │ │ │ +│ ├───────────────────────────────────────────────┤ │ │ +| | Contains the UEFI GOP driver (Graphics Output)| | | +│ │ ┌───────────────────┐ │ │ │ +│ │ │ ROM Header │ │ │ │ +│ │ +───────────────────+ │ │ │ +│ │ │ PCIR Structure │ │ │ │ +│ │ +───────────────────+ │ │ │ +│ │ │ NPDE Structure │ │ │ │ +│ │ └───────────────────┘ │ │ │ +│ │ │ Image data │ │ │ │ +│ │ └───────────────────┘ │ │ │ +│ └───────────────────────────────────────────────┘ │ │ +│ (no gap between images) │ │ +│ ┌───────────────────────────────────────────────┐ │ │ +│ │ First FwSec Image (Type 0xE0) │ │ │ +│ ├───────────────────────────────────────────────┤ │ │ +│ │ ┌───────────────────┐ │ │ │ +│ │ │ ROM Header │ │ │ │ +│ │ +───────────────────+ │ │ │ +│ │ │ PCIR Structure │ │ │ │ +│ │ +───────────────────+ │ │ │ +│ │ │ NPDE Structure │ │ │ │ +│ │ └───────────────────┘ │ │ │ +│ │ │ Image data │ │ │ │ +│ │ └───────────────────┘ │ │ │ +│ └───────────────────────────────────────────────┘ │ │ +│ (no gap between images) │ │ +│ ┌───────────────────────────────────────────────┐ │ │ +│ │ Second FwSec Image (Type 0xE0) │ │ │ +│ ├───────────────────────────────────────────────┤ │ │ +│ │ ┌───────────────────┐ │ │ │ +│ │ │ ROM Header │ │ │ │ +│ │ +───────────────────+ │ │ │ +│ │ │ PCIR Structure │ │ │ │ +│ │ +───────────────────+ │ │ │ +│ │ │ NPDE Structure │ │ │ │ +│ │ └───────────────────┘ │ │ │ +│ │ │ │ │ +│ │ ┌───────────────────┐ │ │ │ +│ │ │ PMU Lookup Table │ <- falcon_data_offset │<─┘ │ +│ │ │ ┌─────────────┐ │ pmu_lookup_table │ │ +│ │ │ │ Entry 0x85 │ │ │ │ +│ │ │ │ FWSEC_PROD │ │ │ │ +│ │ │ └─────────────┘ │ │ │ +│ │ └───────────────────┘ │ │ +│ │ │ │ │ +│ │ │ points to │ │ +│ │ V │ │ +│ │ ┌───────────────────┐ │ │ +│ │ │ FalconUCodeDescV3 │ <- falcon_ucode_offset │ │ +│ │ │ (FWSEC Firmware) │ fwsec_header() │ │ +│ │ └───────────────────┘ │ │ +│ │ │ immediately followed by... │ │ +│ │ V │ │ +│ │ ┌────────────────────────────┐ │ │ +│ │ │ Signatures + FWSEC Ucode │ │ │ +│ │ │ fwsec_sigs(), fwsec_ucode()│ │ │ +│ │ └────────────────────────────┘ │ │ +│ └───────────────────────────────────────────────┘______________________│ + -- 2.43.0
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