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Message-ID: <003801dbb3eb$c435aca0$4ca105e0$@samsung.com>
Date: Wed, 23 Apr 2025 10:05:12 +0900
From: 손신 <shin.son@...sung.com>
To: "'Krzysztof Kozlowski'" <krzk@...nel.org>, "'Sylwester Nawrocki'"
<s.nawrocki@...sung.com>, "'Chanwoo Choi'" <cw00.choi@...sung.com>, "'Alim
Akhtar'" <alim.akhtar@...sung.com>, "'Michael Turquette'"
<mturquette@...libre.com>, "'Stephen Boyd'" <sboyd@...nel.org>, "'Rob
Herring'" <robh@...nel.org>, "'Conor Dooley'" <conor+dt@...nel.org>,
"'Sunyeal Hong'" <sunyeal.hong@...sung.com>
Cc: <linux-samsung-soc@...r.kernel.org>, <linux-clk@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>
Subject: RE: [PATCH 3/3] arm64: dts: exynosautov920: add cpucl0 clock DT
nodes
Hello Krzysztof Kozlowski,
> -----Original Message-----
> From: Krzysztof Kozlowski [mailto:krzk@...nel.org]
> Sent: Tuesday, April 22, 2025 5:00 PM
> To: Shin Son <shin.son@...sung.com>; Sylwester Nawrocki
> <s.nawrocki@...sung.com>; Chanwoo Choi <cw00.choi@...sung.com>; Alim
> Akhtar <alim.akhtar@...sung.com>; Michael Turquette
> <mturquette@...libre.com>; Stephen Boyd <sboyd@...nel.org>; Rob Herring
> <robh@...nel.org>; Conor Dooley <conor+dt@...nel.org>; Sunyeal Hong
> <sunyeal.hong@...sung.com>
> Cc: linux-samsung-soc@...r.kernel.org; linux-clk@...r.kernel.org;
> devicetree@...r.kernel.org; linux-arm-kernel@...ts.infradead.org; linux-
> kernel@...r.kernel.org
> Subject: Re: [PATCH 3/3] arm64: dts: exynosautov920: add cpucl0 clock DT
> nodes
>
> On 18/04/2025 08:15, Shin Son wrote:
> > Add cmu_cpucl0 clocks for switch, cluster, and dbg domains respectively.
> >
> > Signed-off-by: Shin Son <shin.son@...sung.com>
> > ---
> > arch/arm64/boot/dts/exynos/exynosautov920.dtsi | 15 +++++++++++++++
> > 1 file changed, 15 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> > index fc6ac531d597..d1528633adfe 100644
> > --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> > +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> > @@ -582,6 +582,21 @@ pinctrl_aud: pinctrl@...60000 {
> > compatible = "samsung,exynosautov920-pinctrl";
> > reg = <0x1a460000 0x10000>;
> > };
> > +
> > + cmu_cpucl0: clock-controller@...00000 {
> > + compatible = "samsung,exynosautov920-cmu-cpucl0";
> > + reg = <0x1EC00000 0x8000>;
>
> Lowercase hex.
> > + #clock-cells = <1>;
> > +
> > + clocks = <&xtcxo>,
> > + <&cmu_top DOUT_CLKCMU_CPUCL0_SWITCH>,
>
> This looks misaligned.
>
>
> Best regards,
> Krzysztof
Thanks for the quick response.
I'll revise everything you pointed out and send an updated patch shortly.
Best regards,
Shin Son
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