linux-kernel - Re: [PATCH 4/5] arm64: dts: allwinner: a527: add EMAC0 to Radxa A5E board

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Message-ID: <20250424130523.6ceecca3@donnerap.manchester.arm.com>
Date: Thu, 24 Apr 2025 13:05:23 +0100
From: Andre Przywara <andre.przywara@....com>
To: Yixun Lan <dlan@...too.org>
Cc: Andrew Lunn <andrew@...n.ch>, Rob Herring <robh@...nel.org>, Krzysztof
 Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, Chen-Yu
 Tsai <wens@...e.org>, Jernej Skrabec <jernej.skrabec@...il.com>, Samuel
 Holland <samuel@...lland.org>, Maxime Ripard <mripard@...nel.org>, Andrew
 Lunn <andrew+netdev@...n.ch>, "David S. Miller" <davem@...emloft.net>, Eric
 Dumazet <edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>, Paolo
 Abeni <pabeni@...hat.com>, <devicetree@...r.kernel.org>,
 <linux-arm-kernel@...ts.infradead.org>, <linux-sunxi@...ts.linux.dev>,
 <linux-kernel@...r.kernel.org>, <netdev@...r.kernel.org>
Subject: Re: [PATCH 4/5] arm64: dts: allwinner: a527: add EMAC0 to Radxa A5E
 board

On Thu, 24 Apr 2025 10:05:14 +0000
Yixun Lan <dlan@...too.org> wrote:

Hi,

> Hi Andrew, Andre,
> 
> On 01:42 Thu 24 Apr     , Andre Przywara wrote:
> > On Wed, 23 Apr 2025 18:58:37 +0200
> > Andrew Lunn <andrew@...n.ch> wrote:
> > 
> > Hi,
> >   
> > > > +&emac0 {
> > > > +	phy-mode = "rgmii";    
> > > 
> > > Does the PCB have extra long clock lines in order to provide the
> > > needed 2ns delay? I guess not, so this should be rgmii-id.  
> > 
> > That's a good point, and it probably true.
> >   
> > >   
> > > > +	phy-handle = <&ext_rgmii_phy>;
> > > > +
> > > > +	allwinner,tx-delay-ps = <300>;
> > > > +	allwinner,rx-delay-ps = <400>;    
> > > 
> > > These are rather low delays, since the standard requires 2ns. Anyway,
> > > once you change phy-mode, you probably don't need these.  
> >   
> As I tested, drop these two properties making ethernet unable to work,
> there might be some space to improve, but currently I'd leave it for now

Yes, I think we need those delays to be programmed into the syscon clock
register, and have been doing so for years.

> > Those go on top of the main 2ns delay, I guess to accommodate some skew
> > between the RX and TX lines, or to account for extra some PCB delay
> > between clock and data? The vendor BSP kernels/DTs program those board
> > specific values, so we have been following suit for a while, for the
> > previous SoCs as well.
> > I just tried, it also works with some variations of those values, but
> > setting tx-delay to 0 stops communication.
> >   
> I'd not bother to try other combinations, and just stick to vendor's settings

I learned to not rely too much on Allwinner BSP settings ;-)

And it's quite easy to experiment, actually: you can write directly to
0x3000030, for instance using devmem or peekpoke, at Linux runtime. Run
some tests or benchmarks, then try a new setting, without rebooting.

Cheers,
Andre.