linux-kernel - Re: [PATCH v3 3/7] drm/msm/mdp4: register the LVDS PLL as a clock provider

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <b0d81293-af00-4d84-96b4-2a26e1ea8677@quicinc.com>
Date: Thu, 24 Apr 2025 12:41:50 -0700
From: Abhinav Kumar <quic_abhinavk@...cinc.com>
To: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
CC: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
        Rob Clark
	<robdclark@...il.com>, Sean Paul <sean@...rly.run>,
        Marijn Suijten
	<marijn.suijten@...ainline.org>,
        Maarten Lankhorst
	<maarten.lankhorst@...ux.intel.com>,
        Maxime Ripard <mripard@...nel.org>,
        Thomas Zimmermann <tzimmermann@...e.de>,
        David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
        Rob Herring <robh@...nel.org>,
        "Krzysztof
 Kozlowski" <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>,
        "Bjorn
 Andersson" <andersson@...nel.org>,
        Konrad Dybcio <konradybcio@...nel.org>,
        <linux-arm-msm@...r.kernel.org>, <dri-devel@...ts.freedesktop.org>,
        <freedreno@...ts.freedesktop.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>,
        Konrad Dybcio
	<konrad.dybcio@....qualcomm.com>
Subject: Re: [PATCH v3 3/7] drm/msm/mdp4: register the LVDS PLL as a clock
 provider



On 4/24/2025 3:22 AM, Dmitry Baryshkov wrote:
> On Wed, Apr 23, 2025 at 03:54:13PM -0700, Abhinav Kumar wrote:
>>
>>
>> On 2/26/2025 6:25 PM, Dmitry Baryshkov wrote:
>>> The LVDS/LCDC controller uses pixel clock coming from the multimedia
>>> controller (mmcc) rather than using the PLL directly. Stop using LVDS
>>> PLL directly and register it as a clock provider. Use lcdc_clk as a
>>> pixel clock for the LCDC.
>>>
>>> Reviewed-by: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
>>> ---
>>>    drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h          |  2 +-
>>>    drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c |  8 +++++++-
>>>    drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c     | 22 +++++++---------------
>>>    3 files changed, 15 insertions(+), 17 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h
>>> index 142ccb68b435263f91ba1ab27676e426d43e5d84..b8bdc3712c73b14f3547dce3439a895e3d10f193 100644
>>> --- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h
>>> +++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h
>>> @@ -207,6 +207,6 @@ static inline struct drm_encoder *mdp4_dsi_encoder_init(struct drm_device *dev)
>>>    }
>>>    #endif
>>> -struct clk *mpd4_lvds_pll_init(struct drm_device *dev);
>>> +int mpd4_lvds_pll_init(struct drm_device *dev);
>>>    #endif /* __MDP4_KMS_H__ */
>>> diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c
>>> index 8bbc7fb881d599e7d309cc61bda83697fecd253a..db93795916cdaa87ac8e61d3b44c2dadac10fd9e 100644
>>> --- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c
>>> +++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c
>>> @@ -381,7 +381,13 @@ struct drm_encoder *mdp4_lcdc_encoder_init(struct drm_device *dev,
>>>    	drm_encoder_helper_add(encoder, &mdp4_lcdc_encoder_helper_funcs);
>>>    	/* TODO: do we need different pll in other cases? */
>>> -	mdp4_lcdc_encoder->lcdc_clk = mpd4_lvds_pll_init(dev);
>>> +	ret = mpd4_lvds_pll_init(dev);
>>> +	if (ret) {
>>> +		DRM_DEV_ERROR(dev->dev, "failed to register LVDS PLL\n");
>>> +		return ERR_PTR(ret);
>>> +	}
>>> +
>>> +	mdp4_lcdc_encoder->lcdc_clk = devm_clk_get(dev->dev, "lcdc_clk");
>>>    	if (IS_ERR(mdp4_lcdc_encoder->lcdc_clk)) {
>>>    		DRM_DEV_ERROR(dev->dev, "failed to get lvds_clk\n");
>>>    		return ERR_CAST(mdp4_lcdc_encoder->lcdc_clk);
>>
>> Change seems fine to me, one question on the order of changes, DT change has
>> to be merged first otherwise it will fail here?
> 
> It is already semi-broken, as just enabling the PLL is not enough. The
> branch clocks in MMSS are to be toggled / manipulated. As such, it's
> questionable if we need to coordinate or not.
> 

Yes but wouldnt this cause mdp4_lcdc_encoder_init() failure which in 
turn will cause mdp4_kms_init() failure?

So I thought that by merging the DTSI piece first this can be avoided.

>>
>> Will that be managed by co-ordinating with the DT maintainer?
>>
>