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Message-ID: <20250424014120.0d66bd85@minigeek.lan>
Date: Thu, 24 Apr 2025 01:42:41 +0100
From: Andre Przywara <andre.przywara@....com>
To: Andrew Lunn <andrew@...n.ch>
Cc: Yixun Lan <dlan@...too.org>, Rob Herring <robh@...nel.org>, Krzysztof
 Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, Chen-Yu
 Tsai <wens@...e.org>, Jernej Skrabec <jernej.skrabec@...il.com>, Samuel
 Holland <samuel@...lland.org>, Maxime Ripard <mripard@...nel.org>, Andrew
 Lunn <andrew+netdev@...n.ch>, "David S. Miller" <davem@...emloft.net>, Eric
 Dumazet <edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>, Paolo
 Abeni <pabeni@...hat.com>, devicetree@...r.kernel.org,
 linux-arm-kernel@...ts.infradead.org, linux-sunxi@...ts.linux.dev,
 linux-kernel@...r.kernel.org, netdev@...r.kernel.org
Subject: Re: [PATCH 4/5] arm64: dts: allwinner: a527: add EMAC0 to Radxa A5E
 board

On Wed, 23 Apr 2025 18:58:37 +0200
Andrew Lunn <andrew@...n.ch> wrote:

Hi,

> > +&emac0 {
> > +	phy-mode = "rgmii";  
> 
> Does the PCB have extra long clock lines in order to provide the
> needed 2ns delay? I guess not, so this should be rgmii-id.

That's a good point, and it probably true.

> 
> > +	phy-handle = <&ext_rgmii_phy>;
> > +
> > +	allwinner,tx-delay-ps = <300>;
> > +	allwinner,rx-delay-ps = <400>;  
> 
> These are rather low delays, since the standard requires 2ns. Anyway,
> once you change phy-mode, you probably don't need these.

Those go on top of the main 2ns delay, I guess to accommodate some skew
between the RX and TX lines, or to account for extra some PCB delay
between clock and data? The vendor BSP kernels/DTs program those board
specific values, so we have been following suit for a while, for the
previous SoCs as well.
I just tried, it also works with some variations of those values, but
setting tx-delay to 0 stops communication.

Cheers,
Andre

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