[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <z7rklnxuuqnimmc64vcc2b77n6ohdqznek2yxxlmfljvnkqk4c@4dfzdeb2x2ha>
Date: Fri, 25 Apr 2025 20:26:19 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
To: Bryan O'Donoghue <bryan.odonoghue@...aro.org>
Cc: Robert Foss <rfoss@...nel.org>, Todor Tomov <todor.too@...il.com>,
Mauro Carvalho Chehab <mchehab@...nel.org>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, loic.poulain@....qualcomm.com,
vladimir.zapolskiy@...aro.org, krzk@...nel.org,
linux-arm-msm@...r.kernel.org, linux-media@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 1/2] dt-bindings: media: qcom,x1e80100-camss: Fixup
csiphy supply names
On Fri, Apr 25, 2025 at 04:17:33PM +0100, Bryan O'Donoghue wrote:
> Declare a CSIPHY regulator pair 0p8 and 1p2 for each CSIPHY.
>
> Name the inputs based on the voltage so as to have a consistent naming of
> these rails across SoCs and PCBs.
>
> There are no upstream users of this yaml definition yet so this change is
> safe to make.
>
> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@...aro.org>
> ---
> .../bindings/media/qcom,x1e80100-camss.yaml | 52 +++++++++++++++++-----
> 1 file changed, 40 insertions(+), 12 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml b/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml
> index 113565cf2a991a8dcbc20889090e177e8bcadaac..dc7c1a9394c3b547f5e0885bf501ed42dfbeba88 100644
> --- a/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml
> +++ b/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml
> @@ -118,14 +118,6 @@ properties:
> - const: ife1
> - const: top
>
> - vdd-csiphy-0p8-supply:
> - description:
> - Phandle to a 0.8V regulator supply to a PHY.
> -
> - vdd-csiphy-1p2-supply:
> - description:
> - Phandle to 1.8V regulator supply to a PHY.
> -
> ports:
> $ref: /schemas/graph.yaml#/properties/ports
>
> @@ -157,6 +149,30 @@ properties:
> - clock-lanes
> - data-lanes
>
> + vdd-csiphy0-0p8-supply:
> + description: Phandle to a 0.8V regulator supply to csiphy0.
> +
> + vdd-csiphy0-1p2-supply:
> + description: Phandle to a 1.2V regulator supply to csiphy0.
> +
> + vdd-csiphy1-0p8-supply:
> + description: Phandle to a 0.8V regulator supply to csiphy1.
> +
> + vdd-csiphy1-1p2-supply:
> + description: Phandle to a 1.2V regulator supply to csiphy1.
> +
> + vdd-csiphy2-0p8-supply:
> + description: Phandle to a 0.8V regulator supply to csiphy2.
> +
> + vdd-csiphy2-1p2-supply:
> + description: Phandle to a 1.2V regulator supply to csiphy2.
> +
> + vdd-csiphy4-0p8-supply:
> + description: Phandle to a 0.8V regulator supply to csiphy4.
> +
> + vdd-csiphy4-1p2-supply:
> + description: Phandle to a 1.2V regulator supply to csiphy4.
My preference is still for the platform-specific supply names which can
be correlated to the actual SoC pins.
> +
> required:
> - compatible
> - reg
--
With best wishes
Dmitry
Powered by blists - more mailing lists