linux-kernel - Re: [PATCH v5 0/8] Support Multi-frequency scale for UFS

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Message-Id: <D9FZ9U3AEXW4.1I12FX3YQ3JPW@fairphone.com>
Date: Fri, 25 Apr 2025 21:48:04 +0200
From: "Luca Weiss" <luca.weiss@...rphone.com>
To: "Ziqi Chen" <quic_ziqichen@...cinc.com>, <quic_cang@...cinc.com>,
 <bvanassche@....org>, <mani@...nel.org>, <beanhuo@...ron.com>,
 <avri.altman@....com>, <junwoo80.lee@...sung.com>,
 <martin.petersen@...cle.com>, <quic_nguyenb@...cinc.com>,
 <quic_nitirawa@...cinc.com>, <peter.wang@...iatek.com>,
 <quic_rampraka@...cinc.com>
Cc: <linux-arm-msm@...r.kernel.org>, <linux-scsi@...r.kernel.org>, "Neil
 Armstrong" <neil.armstrong@...aro.org>, "Matthias Brugger"
 <matthias.bgg@...il.com>, "AngeloGioacchino Del Regno"
 <angelogioacchino.delregno@...labora.com>, "open list:ARM/Mediatek SoC
 support:Keyword:mediatek" <linux-kernel@...r.kernel.org>, "moderated
 list:ARM/Mediatek SoC support:Keyword:mediatek"
 <linux-arm-kernel@...ts.infradead.org>, "moderated list:ARM/Mediatek SoC
 support:Keyword:mediatek" <linux-mediatek@...ts.infradead.org>
Subject: Re: [PATCH v5 0/8] Support Multi-frequency scale for UFS

Hi Ziqi,

On Thu Feb 13, 2025 at 9:00 AM CET, Ziqi Chen wrote:
> With OPP V2 enabled, devfreq can scale clocks amongst multiple frequency
> plans. However, the gear speed is only toggled between min and max during
> clock scaling. Enable multi-level gear scaling by mapping clock frequencies
> to gear speeds, so that when devfreq scales clock frequencies we can put
> the UFS link at the appropraite gear speeds accordingly.

I believe this series is causing issues on SM6350:

[    0.859449] ufshcd-qcom 1d84000.ufshc: ufs_qcom_freq_to_gear_speed: Unsupported clock freq : 200000000
[    0.886668] ufshcd-qcom 1d84000.ufshc: UNIPRO clk freq 200 MHz not supported
[    0.903791] devfreq 1d84000.ufshc: dvfs failed with (-22) error

That's with this patch, I actually haven't tried without on v6.15-rc3
https://lore.kernel.org/all/20250314-sm6350-ufs-things-v1-2-3600362cc52c@fairphone.com/

I believe the issue appears because core clk and unipro clk rates don't
match on this platform, so this 200 MHz for GCC_UFS_PHY_AXI_CLK is not a
valid unipro clock rate, but for GCC_UFS_PHY_UNIPRO_CORE_CLK it's
specified to 150 MHz in the opp table.

Regards
Luca

>
> This series has been tested on below platforms -
> sm8550 mtp + UFS3.1
> SM8650 MTP + UFS3.1
> SM8750 MTP + UFS4.0