linux-kernel - [PATCH] phy: phy-rockchip-samsung-hdptx: Fix PHY PLL output 50.25MHz error

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Message-ID: <20250425023720.3296069-1-algea.cao@rock-chips.com>
Date: Fri, 25 Apr 2025 10:37:20 +0800
From: Algea Cao <algea.cao@...k-chips.com>
To: vkoul@...nel.org,
	kishon@...nel.org,
	heiko@...ech.de,
	cristian.ciocaltea@...labora.com,
	andy.yan@...k-chips.com
Cc: linux-phy@...ts.infradead.org,
	linux-arm-kernel@...ts.infradead.org,
	linux-rockchip@...ts.infradead.org,
	linux-kernel@...r.kernel.org,
	Algea Cao <algea.cao@...k-chips.com>
Subject: [PATCH] phy: phy-rockchip-samsung-hdptx: Fix PHY PLL output 50.25MHz error

When using HDMI PLL frequency division coefficient at 50.25MHz
that calculated by rk_hdptx_phy_clk_pll_calc(), it is failed to
get PHY LANE lock. Although the calculated values are within the
allowable range of PHY PLL configuration.

So we manually calculated PHY PLL frequency division coefficient
at 50.25Mhz and added it to ropll_tmds_cfg. Manually calculated
value  can make PHY LANE lock normally and output 50.25MHz normally.

Signed-off-by: Algea Cao <algea.cao@...k-chips.com>
---
 drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
index fe7c05748356..77236f012a1f 100644
--- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
+++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
@@ -476,6 +476,8 @@ static const struct ropll_config ropll_tmds_cfg[] = {
 	  1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
 	{ 650000, 162, 162, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 54, 0, 16, 4, 1,
 	  1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
+	{ 502500, 84, 84, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 11, 1, 4, 5,
+	  4, 11, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
 	{ 337500, 0x70, 0x70, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 0x2, 0, 0x01, 5,
 	  1, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
 	{ 400000, 100, 100, 1, 1, 11, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0,
-- 
2.43.0