linux-kernel - [PATCH v2 2/4] arm64: dts: qcom: x1e80100: add bus topology for PCIe domain 3

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Message-Id: <20250425092955.4099677-3-quic_wenbyao@quicinc.com>
Date: Fri, 25 Apr 2025 17:29:53 +0800
From: Wenbin Yao <quic_wenbyao@...cinc.com>
To: catalin.marinas@....com, will@...nel.org,
        linux-arm-kernel@...ts.infradead.org, andersson@...nel.org,
        konradybcio@...nel.org, robh@...nel.org, krzk+dt@...nel.org,
        conor+dt@...nel.org, linux-arm-msm@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Cc: krishna.chundru@....qualcomm.com, quic_vbadigan@...cinc.com,
        quic_mrana@...cinc.com, quic_cang@...cinc.com, quic_qianyu@...cinc.com,
        quic_wenbyao@...cinc.com
Subject: [PATCH v2 2/4] arm64: dts: qcom: x1e80100: add bus topology for PCIe domain 3

From: Qiang Yu <quic_qianyu@...cinc.com>

Add pcie3port node to represent the PCIe bridge of PCIe3 so that PCI slot
voltage rails can be described under this node in the board's dts.

Signed-off-by: Qiang Yu <quic_qianyu@...cinc.com>
Signed-off-by: Wenbin Yao <quic_wenbyao@...cinc.com>
---
 arch/arm64/boot/dts/qcom/x1e80100.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index 46b79fce9..430f9d567 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -3287,6 +3287,17 @@ opp-128000000 {
 					opp-peak-kBps = <15753000 1>;
 				};
 			};
+
+			pcie3port: pcie@0 {
+				device_type = "pci";
+				compatible = "pciclass,0604";
+				reg = <0x0 0x0 0x0 0x0 0x0>;
+				bus-range = <0x01 0xff>;
+
+				#address-cells = <3>;
+				#size-cells = <2>;
+				ranges;
+			};
 		};
 
 		pcie3_phy: phy@...0000 {
-- 
2.34.1