linux-kernel - [PATCH v2 1/2] PCI: Configure root port MPS to hardware maximum during host probing

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Message-Id: <20250425095708.32662-2-18255117159@163.com>
Date: Fri, 25 Apr 2025 17:57:07 +0800
From: Hans Zhang <18255117159@....com>
To: lpieralisi@...nel.org,
	kw@...ux.com,
	bhelgaas@...gle.com,
	heiko@...ech.de,
	thomas.petazzoni@...tlin.com,
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Cc: pali@...nel.org,
	neil.armstrong@...aro.org,
	robh@...nel.org,
	jingoohan1@...il.com,
	khilman@...libre.com,
	jbrunet@...libre.com,
	martin.blumenstingl@...glemail.com,
	linux-pci@...r.kernel.org,
	linux-kernel@...r.kernel.org,
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	Hans Zhang <18255117159@....com>
Subject: [PATCH v2 1/2] PCI: Configure root port MPS to hardware maximum during host probing

Current PCIe initialization logic may leave root ports operating with
non-optimal Maximum Payload Size (MPS) settings. While downstream device
configuration is handled during bus enumeration, root port MPS values
inherited from firmware or hardware defaults might not utilize the full
capabilities supported by the controller hardware. This can result in
suboptimal data transfer efficiency across the PCIe hierarchy.

During host controller probing phase, when PCIe bus tuning is enabled,
the implementation now configures root port MPS settings to their
hardware-supported maximum values. By iterating through bridge devices
under the root bus and identifying PCIe root ports, each port's MPS is set
to 128 << pcie_mpss to match the device's maximum supported payload size.
The Max Read Request Size (MRRS) is subsequently adjusted through existing
companion logic to maintain compatibility with PCIe specifications.

Explicit initialization at host probing stage ensures consistent PCIe
topology configuration before downstream devices perform their own MPS
negotiations. This proactive approach addresses platform-specific
requirements where controller drivers depend on properly initialized root
port settings, while maintaining backward compatibility through
PCIE_BUS_TUNE_OFF conditional checks. Hardware capabilities are fully
utilized without altering existing device negotiation behaviors.

Signed-off-by: Hans Zhang <18255117159@....com>
---
 drivers/pci/probe.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 364fa2a514f8..3973c593fdcf 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -3206,6 +3206,7 @@ EXPORT_SYMBOL_GPL(pci_create_root_bus);
 int pci_host_probe(struct pci_host_bridge *bridge)
 {
 	struct pci_bus *bus, *child;
+	struct pci_dev *dev;
 	int ret;

 	pci_lock_rescan_remove();
@@ -3228,6 +3229,17 @@ int pci_host_probe(struct pci_host_bridge *bridge)
 	 */
 	pci_assign_unassigned_root_bus_resources(bus);

+	if (pcie_bus_config != PCIE_BUS_TUNE_OFF) {
+		/* Configure root ports MPS to be MPSS by default */
+		for_each_pci_bridge(dev, bus) {
+			if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
+				continue;
+
+			pcie_write_mps(dev, 128 << dev->pcie_mpss);
+			pcie_write_mrrs(dev);
+		}
+	}
+
 	list_for_each_entry(child, &bus->children, node)
 		pcie_bus_configure_settings(child);

-- 
2.25.1