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Message-ID: <e6752451-4492-4ae2-9bad-3865c4945dbe@linaro.org>
Date: Fri, 25 Apr 2025 13:59:43 +0200
From: neil.armstrong@...aro.org
To: Hans Zhang <18255117159@....com>, lpieralisi@...nel.org, kw@...ux.com,
bhelgaas@...gle.com, heiko@...ech.de, thomas.petazzoni@...tlin.com,
manivannan.sadhasivam@...aro.org, yue.wang@...ogic.com
Cc: pali@...nel.org, robh@...nel.org, jingoohan1@...il.com,
khilman@...libre.com, jbrunet@...libre.com,
martin.blumenstingl@...glemail.com, linux-pci@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-amlogic@...ts.infradead.org, linux-rockchip@...ts.infradead.org
Subject: Re: [PATCH v2 2/2] PCI: Remove redundant MPS configuration
On 25/04/2025 11:57, Hans Zhang wrote:
> With the PCI core now centrally configuring root port MPS to
> hardware-supported maximums (via 128 << pcie_mpss) during host probing,
> platform-specific MPS adjustments are redundant. This patch removes the
> custom the configuration of the max payload logic to align with the
> standardized initialization flow.
>
> By eliminating redundant code, this change prevents conflicts with global
> PCIe hierarchy tuning policies and reduces maintenance overhead. The Meson
> driver now fully relies on the core PCI framework for MPS configuration,
> ensuring consistency across the PCIe topology while preserving
> hardware-specific MRRS handling.
>
> Signed-off-by: Hans Zhang <18255117159@....com>
> ---
> drivers/pci/controller/dwc/pci-meson.c | 17 -----------------
> drivers/pci/controller/pci-aardvark.c | 2 --
> 2 files changed, 19 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-meson.c b/drivers/pci/controller/dwc/pci-meson.c
> index db9482a113e9..126f38ed453d 100644
> --- a/drivers/pci/controller/dwc/pci-meson.c
> +++ b/drivers/pci/controller/dwc/pci-meson.c
> @@ -261,22 +261,6 @@ static int meson_size_to_payload(struct meson_pcie *mp, int size)
> return fls(size) - 8;
> }
>
> -static void meson_set_max_payload(struct meson_pcie *mp, int size)
> -{
> - struct dw_pcie *pci = &mp->pci;
> - u32 val;
> - u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> - int max_payload_size = meson_size_to_payload(mp, size);
> -
> - val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
> - val &= ~PCI_EXP_DEVCTL_PAYLOAD;
> - dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
> -
> - val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
> - val |= PCIE_CAP_MAX_PAYLOAD_SIZE(max_payload_size);
> - dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
> -}
> -
> static void meson_set_max_rd_req_size(struct meson_pcie *mp, int size)
> {
> struct dw_pcie *pci = &mp->pci;
> @@ -381,7 +365,6 @@ static int meson_pcie_host_init(struct dw_pcie_rp *pp)
>
> pp->bridge->ops = &meson_pci_ops;
>
> - meson_set_max_payload(mp, MAX_PAYLOAD_SIZE);
> meson_set_max_rd_req_size(mp, MAX_READ_REQ_SIZE);
Seems you can also remove meson_set_max_rd_req_size() since it's
done by pcie_write_mrrs()
Neil
>
> return 0;
> diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
> index a29796cce420..d8852892994a 100644
> --- a/drivers/pci/controller/pci-aardvark.c
> +++ b/drivers/pci/controller/pci-aardvark.c
> @@ -549,9 +549,7 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
> reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL);
> reg &= ~PCI_EXP_DEVCTL_RELAX_EN;
> reg &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
> - reg &= ~PCI_EXP_DEVCTL_PAYLOAD;
> reg &= ~PCI_EXP_DEVCTL_READRQ;
> - reg |= PCI_EXP_DEVCTL_PAYLOAD_512B;
> reg |= PCI_EXP_DEVCTL_READRQ_512B;
> advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL);
>
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