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Message-ID:
<PAWPR08MB8909FF04485529558B58BE1D9F872@PAWPR08MB8909.eurprd08.prod.outlook.com>
Date: Sat, 26 Apr 2025 12:42:34 +0000
From: Wathsala Wathawana Vithanage <wathsala.vithanage@....com>
To: Alex Williamson <alex.williamson@...hat.com>
CC: Jason Gunthorpe <jgg@...pe.ca>, "linux-kernel@...r.kernel.org"
<linux-kernel@...r.kernel.org>, nd <nd@....com>, Kevin Tian
<kevin.tian@...el.com>, Philipp Stanner <pstanner@...hat.com>, Yunxiang Li
<Yunxiang.Li@....com>, "Dr. David Alan Gilbert" <linux@...blig.org>, Ankit
Agrawal <ankita@...dia.com>, "open list:VFIO DRIVER" <kvm@...r.kernel.org>,
Dhruv Tripathi <Dhruv.Tripathi@....com>, Honnappa Nagarahalli
<Honnappa.Nagarahalli@....com>, Jeremy Linton <Jeremy.Linton@....com>
Subject: RE: [RFC PATCH] vfio/pci: add PCIe TPH to device feature ioctl
> Having said that, regardless of this proposal or the availability of kernel
> TPH support, a VFIO driver could enable TPH and set an arbitrary ST on the
> MSI-X/ST table or a device-specific location on supported platforms. If the
> driver doesn't have a list of valid STs, it can enumerate 8- or 16-bit STs and
> measure access latencies to determine valid ones.
>
I tested enabling TPH inside a VM with setpci, it turned out that it doesn't
write to TPH control register thankfully because vfio_pci_init_perm_bits()
in host kernel is not setting config write permissions for PCI_EXT_CAP_ID_TPH.
QEMU traps config writes and routes them via vfio_pci_write_config().
So, like how it already handles MSI/MSI-X enablement, TPH enablement
too could be handled by a special handler that does the following.
1. Error out on device specific mode enablement.
2. Check ST-table writes for STs that do not belong to CPUs the VM is bound to.
Then for MSI-X mode, a Quirk could trap and check STs for the #2 case
above.
To make #1 above consistent with TPH cap register, some emulated bits can
be added to mask out availability of device specific mode.
--wathsala
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