linux-kernel - Re: [PATCH v2] PCI: dwc: Set PORT_LOGIC_LINK

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Message-ID: <174577504939.89301.2622778096391890243.b4-ty@linaro.org>
Date: Sun, 27 Apr 2025 23:00:55 +0530
From: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
To: jingoohan1@...il.com,
	lpieralisi@...nel.org,
	kw@...ux.com,
	robh@...nel.org,
	bhelgaas@...gle.com,
	linux-pci@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	Wenbin Yao <quic_wenbyao@...cinc.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
	krishna.chundru@....qualcomm.com,
	quic_vbadigan@...cinc.com,
	quic_mrana@...cinc.com,
	quic_cang@...cinc.com,
	quic_qianyu@...cinc.com
Subject: Re: [PATCH v2] PCI: dwc: Set PORT_LOGIC_LINK_WIDTH to one lane


On Tue, 22 Apr 2025 18:36:23 +0800, Wenbin Yao wrote:
> As per DWC PCIe registers description 4.30a, section 1.13.43, NUM_OF_LANES
> named as PORT_LOGIC_LINK_WIDTH in PCIe DWC driver, is referred to as the
> "Predetermined Number of Lanes" in section 4.2.6.2.1 of the PCI Express
> Base 3.0 Specification, revision 1.0. This section explains the conditions
> need be satisfied for entering Polling.Configuration:
> 
> "Next state is Polling.Configuration after at least 1024 TS1 Ordered Sets
> were transmitted, and all Lanes that detected a Receiver during Detect
> receive eight consecutive training sequences.
> 
> [...]

Applied, thanks!

[1/1] PCI: dwc: Set PORT_LOGIC_LINK_WIDTH to one lane
      commit: 1f7b788a088ee202ecb2eada6bc34d38d63fea19

Best regards,
-- 
Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>