linux-kernel - Re: [PATCH v9 01/13] Documentation: x86: Add AMD Hardware Feedback Interface documentation

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Message-ID: <aA_LZZRVnWdv6IdH@char.us.oracle.com>
Date: Mon, 28 Apr 2025 14:39:33 -0400
From: Konrad Rzeszutek Wilk <konrad.wilk@...cle.com>
To: Mario Limonciello <superm1@...nel.org>
Cc: Hans de Goede <hdegoede@...hat.com>,
        Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>,
        Mario Limonciello <mario.limonciello@....com>,
        Perry Yuan <perry.yuan@....com>, Thomas Gleixner <tglx@...utronix.de>,
        Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
        Dave Hansen <dave.hansen@...ux.intel.com>,
        "maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)" <x86@...nel.org>,
        "H . Peter Anvin" <hpa@...or.com>, Jonathan Corbet <corbet@....net>,
        Huang Rui <ray.huang@....com>,
        "Gautham R . Shenoy" <gautham.shenoy@....com>,
        "Rafael J . Wysocki" <rafael@...nel.org>,
        Viresh Kumar <viresh.kumar@...aro.org>,
        "open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER" <platform-driver-x86@...r.kernel.org>,
        "open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)" <linux-kernel@...r.kernel.org>,
        "open list:DOCUMENTATION" <linux-doc@...r.kernel.org>,
        "open list:AMD PSTATE DRIVER" <linux-pm@...r.kernel.org>,
        Bagas Sanjaya <bagasdotme@...il.com>
Subject: Re: [PATCH v9 01/13] Documentation: x86: Add AMD Hardware Feedback
 Interface documentation

..snip..
> +Implementation details for Linux
> +--------------------------------
> +
> +The implementation of threads scheduling consists of the following steps:
> +
> +1. A thread is spawned and scheduled to the ideal core using the default
> +   heterogeneous scheduling policy.
> +2. The processor profiles thread execution and assigns an enumerated
> +   classification ID.
> +   This classification is communicated to the OS via logical processor
> +   scope MSR.
> +3. During the thread context switch out the operating system consumes the
> +   workload(WL) classification which resides in a logical processor scope MSR.
> +4. The OS triggers the hardware to clear its history by writing to an MSR,
> +   after consuming the WL classification and before switching in the new thread.
> +5. If due to the classification, ranking table, and processor availability,
> +   the thread is not on its ideal processor, the OS will then consider
> +   scheduling the thread on its ideal processor (if available).

Can you expand on 5) please?  The one patch in this patchset that
touches the process file just does an WRMSR.