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Message-ID: <CAAofZF6U_PotxSiXEs+-T5C7E=xA5+7j4=rc-PS-njQMRoCo3g@mail.gmail.com>
Date: Mon, 28 Apr 2025 09:22:57 +0200
From: Marco Crivellari <marco.crivellari@...e.com>
To: "Maciej W. Rozycki" <macro@...am.me.uk>
Cc: Huacai Chen <chenhuacai@...nel.org>, linux-mips@...r.kernel.org,
linux-kernel@...r.kernel.org, Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
Frederic Weisbecker <frederic@...nel.org>, Anna-Maria Behnsen <anna-maria@...utronix.de>,
Thomas Gleixner <tglx@...utronix.de>, Peter Zijlstra <peterz@...radead.org>
Subject: Re: [PATCH v7 1/2] MIPS: Fix idle VS timer enqueue
Hi everyone,
Sorry, I have tested the code only with both the patches applied
(when I also ran the tests with qemu) and I didn't notice my mistake.
I will submit a new version with the correction and the changes
suggested in the other patch, when we find the proper way to do it.
Thank you.
On Mon, Apr 28, 2025 at 3:32 AM Maciej W. Rozycki <macro@...am.me.uk> wrote:
>
> On Sun, 27 Apr 2025, Huacai Chen wrote:
>
> > > +r4k_wait_exit:
> > > + .set mips0
> > > + local_irq_disable
> > > jr ra
> > > - nop
> > > - .set pop
> > > - END(__r4k_wait)
> > > + END(r4k_wait)
> > > + .previous
> > I'm very sorry for the late response, but I think ".previous" should
> > be moved to the second patch.
>
> Indeed; does it even assemble? Correctness aside I'd rather it didn't
> cause someone a problem with bisecting sometime. NB I had no opportunity
> either to look at this version earlier.
>
> Maciej
--
Marco Crivellari
L3 Support Engineer, Technology & Product
marco.crivellari@...e.com
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