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Message-ID: <29c3852c-3218-4b42-bc41-75721a95fccc@quicinc.com>
Date: Mon, 28 Apr 2025 16:06:19 +0800
From: Ziqi Chen <quic_ziqichen@...cinc.com>
To: Luca Weiss <luca.weiss@...rphone.com>, <quic_cang@...cinc.com>,
<bvanassche@....org>, <mani@...nel.org>, <beanhuo@...ron.com>,
<avri.altman@....com>, <junwoo80.lee@...sung.com>,
<martin.petersen@...cle.com>, <quic_nguyenb@...cinc.com>,
<quic_nitirawa@...cinc.com>, <peter.wang@...iatek.com>,
<quic_rampraka@...cinc.com>
CC: <linux-arm-msm@...r.kernel.org>, <linux-scsi@...r.kernel.org>,
"Neil
Armstrong" <neil.armstrong@...aro.org>,
Matthias Brugger
<matthias.bgg@...il.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>,
"open list:ARM/Mediatek SoC
support:Keyword:mediatek" <linux-kernel@...r.kernel.org>,
"moderated
list:ARM/Mediatek SoC support:Keyword:mediatek"
<linux-arm-kernel@...ts.infradead.org>,
"moderated list:ARM/Mediatek SoC
support:Keyword:mediatek" <linux-mediatek@...ts.infradead.org>
Subject: Re: [PATCH v5 0/8] Support Multi-frequency scale for UFS
Hi Luca,
We made changes to fix this special platform issue and verified it can
fix this issue.
Could you help double check if attached 3 patched can fix it from you side?
If it is OK from you side as well, we will submit the final patches to
upstream
Thanks a lot~
BRs
Ziqi
On 4/27/2025 4:14 PM, Ziqi Chen wrote:
> Hi Luca,
>
> Thanks for your report.
> Really, 6350 is a special platform that the UFS_PHY_AXI_CLK doesn't
> match to the UFS_PHY_UNIPRO_CORE_CLK. We already found out the root
> cause and discussing the fix. We will submit change to fix this corner
> case.
>
> BRs
> Ziqi
>
> On 4/26/2025 3:48 AM, Luca Weiss wrote:
>> Hi Ziqi,
>>
>> On Thu Feb 13, 2025 at 9:00 AM CET, Ziqi Chen wrote:
>>> With OPP V2 enabled, devfreq can scale clocks amongst multiple frequency
>>> plans. However, the gear speed is only toggled between min and max
>>> during
>>> clock scaling. Enable multi-level gear scaling by mapping clock
>>> frequencies
>>> to gear speeds, so that when devfreq scales clock frequencies we can put
>>> the UFS link at the appropraite gear speeds accordingly.
>>
>> I believe this series is causing issues on SM6350:
>>
>> [ 0.859449] ufshcd-qcom 1d84000.ufshc: ufs_qcom_freq_to_gear_speed:
>> Unsupported clock freq : 200000000
>> [ 0.886668] ufshcd-qcom 1d84000.ufshc: UNIPRO clk freq 200 MHz not
>> supported
>> [ 0.903791] devfreq 1d84000.ufshc: dvfs failed with (-22) error
>>
>> That's with this patch, I actually haven't tried without on v6.15-rc3
>> https://lore.kernel.org/all/20250314-sm6350-ufs-things-
>> v1-2-3600362cc52c@...rphone.com/
>>
>> I believe the issue appears because core clk and unipro clk rates don't
>> match on this platform, so this 200 MHz for GCC_UFS_PHY_AXI_CLK is not a
>> valid unipro clock rate, but for GCC_UFS_PHY_UNIPRO_CORE_CLK it's
>> specified to 150 MHz in the opp table.
>>
>> Regards
>> Luca
>>
>>>
>>> This series has been tested on below platforms -
>>> sm8550 mtp + UFS3.1
>>> SM8650 MTP + UFS3.1
>>> SM8750 MTP + UFS4.0
>
View attachment "0001-ufs-host-ufs-qcom-Map-OPP-freq-to-UniPro-Core-Clock-.patch" of type "text/plain" (1815 bytes)
View attachment "0002-ufs-host-ufs-qcom-Fix-ufs_qcom_core_clk_ctrl.patch" of type "text/plain" (3813 bytes)
View attachment "0003-ufs-host-ufs-qcom-Fix-ufs_qcom_cfg_timers.patch" of type "text/plain" (3966 bytes)
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