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Message-ID: <a3438b8b-0fd2-454f-a539-39aa7cfcd57b@kernel.org>
Date: Mon, 28 Apr 2025 11:14:33 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Shin Son <shin.son@...sung.com>,
Sylwester Nawrocki <s.nawrocki@...sung.com>,
Chanwoo Choi <cw00.choi@...sung.com>, Alim Akhtar <alim.akhtar@...sung.com>,
Michael Turquette <mturquette@...libre.com>, Stephen Boyd
<sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Sunyeal Hong <sunyeal.hong@...sung.com>
Cc: linux-samsung-soc@...r.kernel.org, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/3] clk: samsung: exynosautov920: add cpucl1/2 clock
support
On 28/04/2025 10:47, Shin Son wrote:
> Register compatible and cmu_info data to support clock CPUCL1/2
> (CPU Cluster 1 and CPU Cluster 2),
> these provide clock for CPUCL1/2_SWTICH/CLUSTER.
>
> These clocks are required early during boot for the CPUs,
> so they are declared using CLK_OF_DECLARE instead of being registered
> through a platform driver.
>
> Signed-off-by: Shin Son <shin.son@...sung.com>
> ---
> drivers/clk/samsung/clk-exynosautov920.c | 208 ++++++++++++++++++++++-
> 1 file changed, 207 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/samsung/clk-exynosautov920.c b/drivers/clk/samsung/clk-exynosautov920.c
> index 8021e0912e50..f8168eed4a66 100644
> --- a/drivers/clk/samsung/clk-exynosautov920.c
> +++ b/drivers/clk/samsung/clk-exynosautov920.c
> @@ -18,7 +18,9 @@
>
> /* NOTE: Must be equal to the last clock ID increased by one */
> #define CLKS_NR_TOP (DOUT_CLKCMU_TAA_NOC + 1)
> -#define CLKS_NR_CPUCL0 (CLK_DOUT_CLUSTER0_PERIPHCLK + 1)
> +#define CLKS_NR_CPUCL0 (CLK_DOUT_CPUCL0_NOCP + 1)
You just added that line a week ago and it is already incorrect? Then it
needs patch on its own explaining what are you fixing.
Best regards,
Krzysztof
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