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Message-ID: <440646ce-f213-47d1-9cb7-799bb53654a2@quicinc.com>
Date: Mon, 28 Apr 2025 16:06:41 +0530
From: Akhil P Oommen <quic_akhilpo@...cinc.com>
To: Abel Vesa <abel.vesa@...aro.org>, Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>
CC: <linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, Johan Hovold <johan+linaro@...nel.org>,
        <stable@...r.kernel.org>
Subject: Re: [PATCH] arm64: dts: qcom: x1e80100: Add GFX power domain to GPU
 clock controller

On 4/23/2025 6:28 PM, Abel Vesa wrote:
> According to documentation, the VDD_GFX is powering up the whole GPU
> subsystem. The VDD_GFX is routed through the RPMh GFX power domain.

No. Majority of the area in GPU Subsystem is under GX domain and the
rest are under various other power domains. IIRC, most of the gpucc
block is under always-on cx domain.

-Akhil.

> 
> So tie the RPMh GFX power domain to the GPU clock controller.
> 
> Cc: stable@...r.kernel.org # 6.11
> Fixes: 721e38301b79 ("arm64: dts: qcom: x1e80100: Add gpu support")
> Signed-off-by: Abel Vesa <abel.vesa@...aro.org>
> ---
>  arch/arm64/boot/dts/qcom/x1e80100.dtsi | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> index 46b79fce92c90d969e3de48bc88e27915d1592bb..96d5ab3c426639b0c0af2458d127e3bbbe41c556 100644
> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> @@ -3873,6 +3873,7 @@ gpucc: clock-controller@...0000 {
>  			clocks = <&bi_tcxo_div2>,
>  				 <&gcc GCC_GPU_GPLL0_CPH_CLK_SRC>,
>  				 <&gcc GCC_GPU_GPLL0_DIV_CPH_CLK_SRC>;
> +			power-domains = <&rpmhpd RPMHPD_GFX>;
>  			#clock-cells = <1>;
>  			#reset-cells = <1>;
>  			#power-domain-cells = <1>;
> 
> ---
> base-commit: 2c9c612abeb38aab0e87d48496de6fd6daafb00b
> change-id: 20250423-x1e80100-add-gpucc-gfx-pd-a51e3ff2d6e1
> 
> Best regards,


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