linux-kernel - RE: [PATCH 2/3] clk: samsung: exynosautov920: add cpucl1/2 clock support

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Message-ID: <02d901dbb82a$fb7493a0$f25dbae0$@samsung.com>
Date: Mon, 28 Apr 2025 19:47:48 +0900
From: 손신 <shin.son@...sung.com>
To: "'Krzysztof Kozlowski'" <krzk@...nel.org>, "'Sylwester Nawrocki'"
	<s.nawrocki@...sung.com>, "'Chanwoo Choi'" <cw00.choi@...sung.com>, "'Alim
 Akhtar'" <alim.akhtar@...sung.com>, "'Michael Turquette'"
	<mturquette@...libre.com>, "'Stephen Boyd'" <sboyd@...nel.org>, "'Rob
 Herring'" <robh@...nel.org>, "'Conor Dooley'" <conor+dt@...nel.org>,
	"'Sunyeal Hong'" <sunyeal.hong@...sung.com>
Cc: <linux-samsung-soc@...r.kernel.org>, <linux-clk@...r.kernel.org>,
	<devicetree@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>,
	<linux-kernel@...r.kernel.org>
Subject: RE: [PATCH 2/3] clk: samsung: exynosautov920: add cpucl1/2 clock
 support

Hello, Krzysztof Kozlowski.

> -----Original Message-----
> From: Krzysztof Kozlowski [mailto:krzk@...nel.org]
> Sent: Monday, April 28, 2025 6:15 PM
> To: Shin Son <shin.son@...sung.com>; Sylwester Nawrocki
> <s.nawrocki@...sung.com>; Chanwoo Choi <cw00.choi@...sung.com>; Alim
> Akhtar <alim.akhtar@...sung.com>; Michael Turquette
> <mturquette@...libre.com>; Stephen Boyd <sboyd@...nel.org>; Rob Herring
> <robh@...nel.org>; Conor Dooley <conor+dt@...nel.org>; Sunyeal Hong
> <sunyeal.hong@...sung.com>
> Cc: linux-samsung-soc@...r.kernel.org; linux-clk@...r.kernel.org;
> devicetree@...r.kernel.org; linux-arm-kernel@...ts.infradead.org; linux-
> kernel@...r.kernel.org
> Subject: Re: [PATCH 2/3] clk: samsung: exynosautov920: add cpucl1/2 clock
> support
> 
> On 28/04/2025 10:47, Shin Son wrote:
> > Register compatible and cmu_info data to support clock CPUCL1/2 (CPU
> > Cluster 1 and CPU Cluster 2), these provide clock for
> > CPUCL1/2_SWTICH/CLUSTER.
> >
> > These clocks are required early during boot for the CPUs, so they are
> > declared using CLK_OF_DECLARE instead of being registered through a
> > platform driver.
> >
> > Signed-off-by: Shin Son <shin.son@...sung.com>
> > ---
> >  drivers/clk/samsung/clk-exynosautov920.c | 208
> > ++++++++++++++++++++++-
> >  1 file changed, 207 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/clk/samsung/clk-exynosautov920.c
> > b/drivers/clk/samsung/clk-exynosautov920.c
> > index 8021e0912e50..f8168eed4a66 100644
> > --- a/drivers/clk/samsung/clk-exynosautov920.c
> > +++ b/drivers/clk/samsung/clk-exynosautov920.c
> > @@ -18,7 +18,9 @@
> >
> >  /* NOTE: Must be equal to the last clock ID increased by one */
> >  #define CLKS_NR_TOP			(DOUT_CLKCMU_TAA_NOC + 1)
> > -#define CLKS_NR_CPUCL0			(CLK_DOUT_CLUSTER0_PERIPHCLK + 1)
> > +#define CLKS_NR_CPUCL0			(CLK_DOUT_CPUCL0_NOCP + 1)
> 
> 
> You just added that line a week ago and it is already incorrect? Then it
> needs patch on its own explaining what are you fixing.
> 
> 
> Best regards,
> Krzysztof

Understood. I will separate the fix into its own patch and resend it.

Best regards,
Shin Son