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Message-ID: <174593886824.4084075.3272169793165208261.robh@kernel.org>
Date: Tue, 29 Apr 2025 10:01:12 -0500
From: "Rob Herring (Arm)" <robh@...nel.org>
To: Thierry Bultel <thierry.bultel.yh@...renesas.com>
Cc: Geert Uytterhoeven <geert+renesas@...der.be>, geert@...ux-m68k.org,
paul.barker.ct@...renesas.com, linux-kernel@...r.kernel.org,
linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
linux-renesas-soc@...r.kernel.org, thierry.bultel@...atsea.fr
Subject: Re: [PATCH v8 03/11] dt-bindings: clock: Add cpg for the Renesas
RZ/T2H SoC
On Tue, 29 Apr 2025 10:19:45 +0200, Thierry Bultel wrote:
> Document RZ/T2H (a.k.a r9a09g077) cpg-mssr (Clock Pulse Generator) binding.
>
> Signed-off-by: Thierry Bultel <thierry.bultel.yh@...renesas.com>
> ---
> Changes v7->v8:
> - extra parenthesis
> - added loco
> - renesas-cpg-mssr.h: removed unused clocks, added a macro for mstp
> Changes v6->v7:
> - Add description for reg property
> Changes v5->v6:
> - Set clock minItem constraint
> - Moved additionalProperties after 'allOf' section
> Changes v4->v5:
> - Set reg minItems and maxItems defaults at top level
> Changes v3->v4:
> - Handle maxItems and clocks names properly in schema.
> ---
> .../bindings/clock/renesas,cpg-mssr.yaml | 58 ++++++++++++++-----
> .../clock/renesas,r9a09g077-cpg-mssr.h | 48 +++++++++++++++
> 2 files changed, 90 insertions(+), 16 deletions(-)
> create mode 100644 include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
>
Reviewed-by: Rob Herring (Arm) <robh@...nel.org>
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